diff --git a/llvm/lib/Target/Hexagon/Hexagon.td b/llvm/lib/Target/Hexagon/Hexagon.td index 265f80fa3399..31e08cc1b043 100644 --- a/llvm/lib/Target/Hexagon/Hexagon.td +++ b/llvm/lib/Target/Hexagon/Hexagon.td @@ -52,6 +52,8 @@ def FeatureMemops: SubtargetFeature<"memops", "UseMemops", "true", "Use memop instructions">; def FeatureNVJ: SubtargetFeature<"nvj", "UseNewValueJumps", "true", "Support for new-value jumps", [FeaturePackets]>; +def FeatureNVS: SubtargetFeature<"nvs", "UseNewValueStores", "true", + "Support for new-value stores", [FeaturePackets]>; def FeatureDuplex: SubtargetFeature<"duplex", "EnableDuplex", "true", "Enable generation of duplex instruction">; def FeatureReservedR19: SubtargetFeature<"reserved-r19", "ReservedR19", @@ -321,23 +323,28 @@ class Proc; + FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS, + FeaturePackets]>; def : Proc<"hexagonv5", HexagonModelV4, [ArchV4, ArchV5, - FeatureDuplex, FeatureMemops, FeatureNVJ, FeaturePackets]>; + FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS, + FeaturePackets]>; def : Proc<"hexagonv55", HexagonModelV55, [ArchV4, ArchV5, ArchV55, - FeatureDuplex, FeatureMemops, FeatureNVJ, FeaturePackets]>; + FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS, + FeaturePackets]>; def : Proc<"hexagonv60", HexagonModelV60, [ArchV4, ArchV5, ArchV55, ArchV60, - FeatureDuplex, FeatureMemops, FeatureNVJ, FeaturePackets]>; + FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS, + FeaturePackets]>; def : Proc<"hexagonv62", HexagonModelV62, [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, - FeatureDuplex, FeatureMemops, FeatureNVJ, FeaturePackets]>; + FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS, + FeaturePackets]>; def : Proc<"hexagonv65", HexagonModelV65, [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, FeatureDuplex, FeatureMemNoShuf, FeatureMemops, FeatureNVJ, - FeaturePackets]>; + FeatureNVS, FeaturePackets]>; //===----------------------------------------------------------------------===// // Declare the target which we are implementing diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index 4086c6cfb810..34b07c63d9f5 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -2983,6 +2983,9 @@ bool HexagonInstrInfo::mayBeCurLoad(const MachineInstr &MI) const { // Returns true, if a ST insn can be promoted to a new-value store. bool HexagonInstrInfo::mayBeNewStore(const MachineInstr &MI) const { + if (MI.mayStore() && !Subtarget.useNewValueStores()) + return false; + const uint64_t F = MI.getDesc().TSFlags; return (F >> HexagonII::mayNVStorePos) & HexagonII::mayNVStoreMask; } diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.h b/llvm/lib/Target/Hexagon/HexagonSubtarget.h index f6111b716ad2..b8f7db6ae20e 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.h +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.h @@ -54,6 +54,7 @@ class HexagonSubtarget : public HexagonGenSubtargetInfo { bool UseMemops = false; bool UsePackets = false; bool UseNewValueJumps = false; + bool UseNewValueStores = false; bool HasMemNoShuf = false; bool EnableDuplex = false; @@ -155,6 +156,7 @@ public: bool useMemops() const { return UseMemops; } bool usePackets() const { return UsePackets; } bool useNewValueJumps() const { return UseNewValueJumps; } + bool useNewValueStores() const { return UseNewValueStores; } bool modeIEEERndNear() const { return ModeIEEERndNear; } bool useHVXOps() const { return HexagonHVXVersion > Hexagon::ArchEnum::V4; }