forked from OSchip/llvm-project
Replace NEON vabdl, vaba, and vabal intrinsics with combinations of the
vabd intrinsic and add and/or zext operations. In the case of vaba, this also avoids the need for a DAG combine pattern to combine vabd with add. Update tests. Auto-upgrade the old intrinsics. llvm-svn: 112941
This commit is contained in:
Bob Wilson
parent
335e16bad4
commit
f65c9ef720
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@ -176,14 +176,6 @@ let TargetPrefix = "arm" in {
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// Vector Absolute Differences.
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def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
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def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
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def int_arm_neon_vabdls : Neon_2Arg_Long_Intrinsic;
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def int_arm_neon_vabdlu : Neon_2Arg_Long_Intrinsic;
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// Vector Absolute Difference and Accumulate.
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def int_arm_neon_vabas : Neon_3Arg_Intrinsic;
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def int_arm_neon_vabau : Neon_3Arg_Intrinsic;
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def int_arm_neon_vabals : Neon_3Arg_Long_Intrinsic;
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def int_arm_neon_vabalu : Neon_3Arg_Long_Intrinsic;
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// Vector Pairwise Add.
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def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
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@ -4293,28 +4293,11 @@ SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
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/// operands.
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static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
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TargetLowering::DAGCombinerInfo &DCI) {
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SelectionDAG &DAG = DCI.DAG;
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// fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
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if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
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SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
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if (Result.getNode()) return Result;
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}
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// fold (add (arm_neon_vabd a, b) c) -> (arm_neon_vaba c, a, b)
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EVT VT = N->getValueType(0);
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if (N0.getOpcode() == ISD::INTRINSIC_WO_CHAIN && VT.isInteger()) {
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unsigned IntNo = cast<ConstantSDNode>(N0.getOperand(0))->getZExtValue();
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if (IntNo == Intrinsic::arm_neon_vabds)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), VT,
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DAG.getConstant(Intrinsic::arm_neon_vabas, MVT::i32),
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N1, N0.getOperand(1), N0.getOperand(2));
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if (IntNo == Intrinsic::arm_neon_vabdu)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), VT,
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DAG.getConstant(Intrinsic::arm_neon_vabau, MVT::i32),
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N1, N0.getOperand(1), N0.getOperand(2));
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}
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return SDValue();
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}
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@ -1288,6 +1288,24 @@ class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
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(ResTy (NEONvduplane (OpTy DPR_8:$src3),
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imm:$lane)))))))]>;
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// Neon Intrinsic-Op instructions (VABA): double- and quad-register.
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class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
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InstrItinClass itin, string OpcodeStr, string Dt,
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ValueType Ty, Intrinsic IntOp, SDNode OpNode>
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: N3V<op24, op23, op21_20, op11_8, 0, op4,
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(outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
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OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
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[(set DPR:$dst, (Ty (OpNode DPR:$src1,
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(Ty (IntOp (Ty DPR:$src2), (Ty DPR:$src3))))))]>;
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class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
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InstrItinClass itin, string OpcodeStr, string Dt,
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ValueType Ty, Intrinsic IntOp, SDNode OpNode>
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: N3V<op24, op23, op21_20, op11_8, 1, op4,
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(outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), N3RegFrm, itin,
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OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
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[(set QPR:$dst, (Ty (OpNode QPR:$src1,
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(Ty (IntOp (Ty QPR:$src2), (Ty QPR:$src3))))))]>;
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// Neon 3-argument intrinsics, both double- and quad-register.
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// The destination register is also used as the first source operand register.
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class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
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@ -1342,6 +1360,17 @@ class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
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(TyD (NEONvduplane (TyD DPR_8:$src3),
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imm:$lane))))))]>;
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// Long Intrinsic-Op vector operations with explicit extend (VABAL).
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class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
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InstrItinClass itin, string OpcodeStr, string Dt,
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ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
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SDNode OpNode>
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: N3V<op24, op23, op21_20, op11_8, 0, op4,
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(outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
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OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
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[(set QPR:$dst, (OpNode (TyQ QPR:$src1),
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(TyQ (ExtOp (TyD (IntOp (TyD DPR:$src2),
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(TyD DPR:$src3)))))))]>;
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// Neon Long 3-argument intrinsic. The destination register is
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// a quad-register and is also used as the first source operand register.
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@ -1433,6 +1462,19 @@ class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
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let isCommutable = Commutable;
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}
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// Long 3-register intrinsics with explicit extend (VABDL).
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class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
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InstrItinClass itin, string OpcodeStr, string Dt,
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ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
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bit Commutable>
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: N3V<op24, op23, op21_20, op11_8, 0, op4,
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(outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
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OpcodeStr, Dt, "$dst, $src1, $src2", "",
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[(set QPR:$dst, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$src1),
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(TyD DPR:$src2))))))]> {
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let isCommutable = Commutable;
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}
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// Long 3-register intrinsics.
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class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
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InstrItinClass itin, string OpcodeStr, string Dt,
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@ -1918,6 +1960,21 @@ multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
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v8i16, v8i8, IntOp, Commutable>;
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}
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// ....with explicit extend (VABDL).
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multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
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InstrItinClass itin, string OpcodeStr, string Dt,
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Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
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def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
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OpcodeStr, !strconcat(Dt, "8"),
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v8i16, v8i8, IntOp, ExtOp, Commutable>;
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def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
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OpcodeStr, !strconcat(Dt, "16"),
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v4i32, v4i16, IntOp, ExtOp, Commutable>;
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def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
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OpcodeStr, !strconcat(Dt, "32"),
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v2i64, v2i32, IntOp, ExtOp, Commutable>;
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}
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// Neon Wide 3-register vector intrinsics,
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// source operand element sizes of 8, 16 and 32 bits:
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@ -1975,6 +2032,29 @@ multiclass N3VMulOpSL_HS<bits<4> op11_8,
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mul, ShOp>;
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}
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// Neon Intrinsic-Op vector operations,
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// element sizes of 8, 16 and 32 bits:
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multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
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InstrItinClass itinD, InstrItinClass itinQ,
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string OpcodeStr, string Dt, Intrinsic IntOp,
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SDNode OpNode> {
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// 64-bit vector types.
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def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
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OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
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def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
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OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
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def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
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OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
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// 128-bit vector types.
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def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
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OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
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def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
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OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
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def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
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OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
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}
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// Neon 3-argument intrinsics,
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// element sizes of 8, 16 and 32 bits:
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multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
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@ -2050,6 +2130,21 @@ multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
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OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
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}
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// ....with explicit extend (VABAL).
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multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
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InstrItinClass itin, string OpcodeStr, string Dt,
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Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
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def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
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OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
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IntOp, ExtOp, OpNode>;
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def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
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OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
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IntOp, ExtOp, OpNode>;
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def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
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OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
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IntOp, ExtOp, OpNode>;
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}
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// Neon 2-register vector intrinsics,
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// element sizes of 8, 16 and 32 bits:
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@ -2765,32 +2860,32 @@ def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
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// VABD : Vector Absolute Difference
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defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
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IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
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"vabd", "s", int_arm_neon_vabds, 0>;
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"vabd", "s", int_arm_neon_vabds, 1>;
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defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
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IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
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"vabd", "u", int_arm_neon_vabdu, 0>;
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"vabd", "u", int_arm_neon_vabdu, 1>;
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def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
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"vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 0>;
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"vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
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def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
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"vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 0>;
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"vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
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// VABDL : Vector Absolute Difference Long (Q = | D - D |)
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defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VSUBi4Q, IIC_VSUBi4Q,
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"vabdl", "s", int_arm_neon_vabdls, 0>;
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defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VSUBi4Q, IIC_VSUBi4Q,
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"vabdl", "u", int_arm_neon_vabdlu, 0>;
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defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
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"vabdl", "s", int_arm_neon_vabds, zext, 1>;
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defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
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"vabdl", "u", int_arm_neon_vabdu, zext, 1>;
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// VABA : Vector Absolute Difference and Accumulate
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defm VABAs : N3VInt3_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
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"vaba", "s", int_arm_neon_vabas>;
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defm VABAu : N3VInt3_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
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"vaba", "u", int_arm_neon_vabau>;
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defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
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"vaba", "s", int_arm_neon_vabds, add>;
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defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
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"vaba", "u", int_arm_neon_vabdu, add>;
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// VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
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defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, IIC_VABAD, IIC_VABAD,
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"vabal", "s", int_arm_neon_vabals>;
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defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, IIC_VABAD, IIC_VABAD,
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"vabal", "u", int_arm_neon_vabalu>;
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defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
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"vabal", "s", int_arm_neon_vabds, zext, add>;
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defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
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"vabal", "u", int_arm_neon_vabdu, zext, add>;
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// Vector Maximum and Minimum.
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@ -81,21 +81,21 @@ static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) {
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} else if (Name.compare(5, 9, "arm.neon.", 9) == 0) {
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if (((Name.compare(14, 5, "vmovl", 5) == 0 ||
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Name.compare(14, 5, "vaddl", 5) == 0 ||
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Name.compare(14, 5, "vsubl", 5) == 0) &&
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(Name.compare(19, 2, "s.", 2) == 0 ||
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Name.compare(19, 2, "u.", 2) == 0)) ||
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((Name.compare(14, 5, "vaddw", 5) == 0 ||
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Name.compare(14, 5, "vsubw", 5) == 0) &&
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(Name.compare(19, 2, "s.", 2) == 0 ||
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Name.compare(19, 2, "u.", 2) == 0)) ||
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((Name.compare(14, 5, "vmull", 5) == 0 ||
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Name.compare(14, 5, "vsubl", 5) == 0 ||
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Name.compare(14, 5, "vaddw", 5) == 0 ||
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Name.compare(14, 5, "vsubw", 5) == 0 ||
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Name.compare(14, 5, "vmull", 5) == 0 ||
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Name.compare(14, 5, "vmlal", 5) == 0 ||
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Name.compare(14, 5, "vmlsl", 5) == 0) &&
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Name.compare(14, 5, "vmlsl", 5) == 0 ||
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Name.compare(14, 5, "vabdl", 5) == 0 ||
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Name.compare(14, 5, "vabal", 5) == 0) &&
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(Name.compare(19, 2, "s.", 2) == 0 ||
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Name.compare(19, 2, "u.", 2) == 0)) ||
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(Name.compare(14, 4, "vaba", 4) == 0 &&
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(Name.compare(18, 2, "s.", 2) == 0 ||
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Name.compare(18, 2, "u.", 2) == 0)) ||
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(Name.compare(14, 6, "vmovn.", 6) == 0)) {
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// Calls to these are transformed into IR without intrinsics.
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@ -391,6 +391,35 @@ static void ExtendNEONArgs(CallInst *CI, Value *Arg0, Value *Arg1,
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}
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}
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/// CallVABD - As part of expanding a call to one of the old NEON vabdl, vaba,
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/// or vabal intrinsics, construct a call to a vabd intrinsic. Examine the
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/// name of the old intrinsic to determine whether to use a signed or unsigned
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/// vabd intrinsic. Get the type from the old call instruction, adjusted for
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/// half-size vector elements if the old intrinsic was vabdl or vabal.
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static Instruction *CallVABD(CallInst *CI, Value *Arg0, Value *Arg1) {
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Function *F = CI->getCalledFunction();
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const std::string& Name = F->getName();
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bool isLong = (Name.at(18) == 'l');
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bool isSigned = (Name.at(isLong ? 19 : 18) == 's');
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Intrinsic::ID intID;
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if (isSigned)
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intID = Intrinsic::arm_neon_vabds;
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else
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intID = Intrinsic::arm_neon_vabdu;
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const Type *Ty = CI->getType();
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if (isLong)
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Ty = VectorType::getTruncatedElementVectorType(cast<const VectorType>(Ty));
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Function *VABD = Intrinsic::getDeclaration(F->getParent(), intID, &Ty, 1);
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Value *Operands[2];
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Operands[0] = Arg0;
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Operands[1] = Arg1;
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return CallInst::Create(VABD, Operands, Operands+2,
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"upgraded."+CI->getName(), CI);
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}
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|
||||
// UpgradeIntrinsicCall - Upgrade a call to an old intrinsic to be a call the
|
||||
// upgraded intrinsic. All argument and return casting must be provided in
|
||||
// order to seamlessly integrate with existing context.
|
||||
|
|
@ -434,6 +463,15 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
|
|||
Instruction *MulI = BinaryOperator::CreateMul(V0, V1, "", CI);
|
||||
NewI = BinaryOperator::CreateSub(CI->getArgOperand(0), MulI,
|
||||
"upgraded."+CI->getName(), CI);
|
||||
} else if (Name.compare(14, 4, "vabd", 4) == 0) {
|
||||
NewI = CallVABD(CI, CI->getArgOperand(0), CI->getArgOperand(1));
|
||||
NewI = new ZExtInst(NewI, CI->getType(), "upgraded."+CI->getName(), CI);
|
||||
} else if (Name.compare(14, 4, "vaba", 4) == 0) {
|
||||
NewI = CallVABD(CI, CI->getArgOperand(1), CI->getArgOperand(2));
|
||||
if (Name.at(18) == 'l')
|
||||
NewI = new ZExtInst(NewI, CI->getType(), "", CI);
|
||||
NewI = BinaryOperator::CreateAdd(CI->getArgOperand(0), NewI,
|
||||
"upgraded."+CI->getName(), CI);
|
||||
} else if (Name.compare(14, 6, "vmovn.", 6) == 0) {
|
||||
NewI = new TruncInst(CI->getArgOperand(0), CI->getType(),
|
||||
"upgraded." + CI->getName(), CI);
|
||||
|
|
@ -675,7 +713,7 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
|
|||
}
|
||||
|
||||
switch (NewFn->getIntrinsicID()) {
|
||||
default: llvm_unreachable("Unknown function for CallInst upgrade.");
|
||||
default: llvm_unreachable("Unknown function for CallInst upgrade.");
|
||||
case Intrinsic::arm_neon_vld1:
|
||||
case Intrinsic::arm_neon_vld2:
|
||||
case Intrinsic::arm_neon_vld3:
|
||||
|
|
|
|||
|
|
@ -126,6 +126,44 @@
|
|||
; CHECK-NEXT: mul <2 x i64>
|
||||
; CHECK-NEXT: sub <2 x i64>
|
||||
|
||||
; vaba should be auto-upgraded to vabd + add
|
||||
|
||||
; CHECK: vabas32
|
||||
; CHECK-NOT: arm.neon.vabas.v2i32
|
||||
; CHECK: arm.neon.vabds.v2i32
|
||||
; CHECK-NEXT: add <2 x i32>
|
||||
|
||||
; CHECK: vabaQu8
|
||||
; CHECK-NOT: arm.neon.vabau.v16i8
|
||||
; CHECK: arm.neon.vabdu.v16i8
|
||||
; CHECK-NEXT: add <16 x i8>
|
||||
|
||||
; vabal should be auto-upgraded to vabd with zext + add
|
||||
|
||||
; CHECK: vabals16
|
||||
; CHECK-NOT: arm.neon.vabals.v4i32
|
||||
; CHECK: arm.neon.vabds.v4i16
|
||||
; CHECK-NEXT: zext <4 x i16>
|
||||
; CHECK-NEXT: add <4 x i32>
|
||||
|
||||
; CHECK: vabalu32
|
||||
; CHECK-NOT: arm.neon.vabalu.v2i64
|
||||
; CHECK: arm.neon.vabdu.v2i32
|
||||
; CHECK-NEXT: zext <2 x i32>
|
||||
; CHECK-NEXT: add <2 x i64>
|
||||
|
||||
; vabdl should be auto-upgraded to vabd with zext
|
||||
|
||||
; CHECK: vabdls8
|
||||
; CHECK-NOT: arm.neon.vabdls.v8i16
|
||||
; CHECK: arm.neon.vabds.v8i8
|
||||
; CHECK-NEXT: zext <8 x i8>
|
||||
|
||||
; CHECK: vabdlu16
|
||||
; CHECK-NOT: arm.neon.vabdlu.v4i32
|
||||
; CHECK: arm.neon.vabdu.v4i16
|
||||
; CHECK-NEXT: zext <4 x i16>
|
||||
|
||||
; vmovn should be auto-upgraded to trunc
|
||||
|
||||
; CHECK: vmovni16
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -6,8 +6,9 @@ define <8 x i8> @vabas8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
|
|||
%tmp1 = load <8 x i8>* %A
|
||||
%tmp2 = load <8 x i8>* %B
|
||||
%tmp3 = load <8 x i8>* %C
|
||||
%tmp4 = call <8 x i8> @llvm.arm.neon.vabas.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3)
|
||||
ret <8 x i8> %tmp4
|
||||
%tmp4 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3)
|
||||
%tmp5 = add <8 x i8> %tmp1, %tmp4
|
||||
ret <8 x i8> %tmp5
|
||||
}
|
||||
|
||||
define <4 x i16> @vabas16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
|
||||
|
|
@ -16,8 +17,9 @@ define <4 x i16> @vabas16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
|
|||
%tmp1 = load <4 x i16>* %A
|
||||
%tmp2 = load <4 x i16>* %B
|
||||
%tmp3 = load <4 x i16>* %C
|
||||
%tmp4 = call <4 x i16> @llvm.arm.neon.vabas.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3)
|
||||
ret <4 x i16> %tmp4
|
||||
%tmp4 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3)
|
||||
%tmp5 = add <4 x i16> %tmp1, %tmp4
|
||||
ret <4 x i16> %tmp5
|
||||
}
|
||||
|
||||
define <2 x i32> @vabas32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
|
||||
|
|
@ -26,8 +28,9 @@ define <2 x i32> @vabas32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
|
|||
%tmp1 = load <2 x i32>* %A
|
||||
%tmp2 = load <2 x i32>* %B
|
||||
%tmp3 = load <2 x i32>* %C
|
||||
%tmp4 = call <2 x i32> @llvm.arm.neon.vabas.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3)
|
||||
ret <2 x i32> %tmp4
|
||||
%tmp4 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3)
|
||||
%tmp5 = add <2 x i32> %tmp1, %tmp4
|
||||
ret <2 x i32> %tmp5
|
||||
}
|
||||
|
||||
define <8 x i8> @vabau8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
|
||||
|
|
@ -36,8 +39,9 @@ define <8 x i8> @vabau8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
|
|||
%tmp1 = load <8 x i8>* %A
|
||||
%tmp2 = load <8 x i8>* %B
|
||||
%tmp3 = load <8 x i8>* %C
|
||||
%tmp4 = call <8 x i8> @llvm.arm.neon.vabau.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3)
|
||||
ret <8 x i8> %tmp4
|
||||
%tmp4 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3)
|
||||
%tmp5 = add <8 x i8> %tmp1, %tmp4
|
||||
ret <8 x i8> %tmp5
|
||||
}
|
||||
|
||||
define <4 x i16> @vabau16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
|
||||
|
|
@ -46,8 +50,9 @@ define <4 x i16> @vabau16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
|
|||
%tmp1 = load <4 x i16>* %A
|
||||
%tmp2 = load <4 x i16>* %B
|
||||
%tmp3 = load <4 x i16>* %C
|
||||
%tmp4 = call <4 x i16> @llvm.arm.neon.vabau.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3)
|
||||
ret <4 x i16> %tmp4
|
||||
%tmp4 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3)
|
||||
%tmp5 = add <4 x i16> %tmp1, %tmp4
|
||||
ret <4 x i16> %tmp5
|
||||
}
|
||||
|
||||
define <2 x i32> @vabau32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
|
||||
|
|
@ -56,8 +61,9 @@ define <2 x i32> @vabau32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
|
|||
%tmp1 = load <2 x i32>* %A
|
||||
%tmp2 = load <2 x i32>* %B
|
||||
%tmp3 = load <2 x i32>* %C
|
||||
%tmp4 = call <2 x i32> @llvm.arm.neon.vabau.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3)
|
||||
ret <2 x i32> %tmp4
|
||||
%tmp4 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3)
|
||||
%tmp5 = add <2 x i32> %tmp1, %tmp4
|
||||
ret <2 x i32> %tmp5
|
||||
}
|
||||
|
||||
define <16 x i8> @vabaQs8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
|
||||
|
|
@ -66,8 +72,9 @@ define <16 x i8> @vabaQs8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind
|
|||
%tmp1 = load <16 x i8>* %A
|
||||
%tmp2 = load <16 x i8>* %B
|
||||
%tmp3 = load <16 x i8>* %C
|
||||
%tmp4 = call <16 x i8> @llvm.arm.neon.vabas.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> %tmp3)
|
||||
ret <16 x i8> %tmp4
|
||||
%tmp4 = call <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8> %tmp2, <16 x i8> %tmp3)
|
||||
%tmp5 = add <16 x i8> %tmp1, %tmp4
|
||||
ret <16 x i8> %tmp5
|
||||
}
|
||||
|
||||
define <8 x i16> @vabaQs16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
|
||||
|
|
@ -76,8 +83,9 @@ define <8 x i16> @vabaQs16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind
|
|||
%tmp1 = load <8 x i16>* %A
|
||||
%tmp2 = load <8 x i16>* %B
|
||||
%tmp3 = load <8 x i16>* %C
|
||||
%tmp4 = call <8 x i16> @llvm.arm.neon.vabas.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> %tmp3)
|
||||
ret <8 x i16> %tmp4
|
||||
%tmp4 = call <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp3)
|
||||
%tmp5 = add <8 x i16> %tmp1, %tmp4
|
||||
ret <8 x i16> %tmp5
|
||||
}
|
||||
|
||||
define <4 x i32> @vabaQs32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
|
||||
|
|
@ -86,8 +94,9 @@ define <4 x i32> @vabaQs32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind
|
|||
%tmp1 = load <4 x i32>* %A
|
||||
%tmp2 = load <4 x i32>* %B
|
||||
%tmp3 = load <4 x i32>* %C
|
||||
%tmp4 = call <4 x i32> @llvm.arm.neon.vabas.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> %tmp3)
|
||||
ret <4 x i32> %tmp4
|
||||
%tmp4 = call <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32> %tmp2, <4 x i32> %tmp3)
|
||||
%tmp5 = add <4 x i32> %tmp1, %tmp4
|
||||
ret <4 x i32> %tmp5
|
||||
}
|
||||
|
||||
define <16 x i8> @vabaQu8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
|
||||
|
|
@ -96,8 +105,9 @@ define <16 x i8> @vabaQu8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind
|
|||
%tmp1 = load <16 x i8>* %A
|
||||
%tmp2 = load <16 x i8>* %B
|
||||
%tmp3 = load <16 x i8>* %C
|
||||
%tmp4 = call <16 x i8> @llvm.arm.neon.vabau.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> %tmp3)
|
||||
ret <16 x i8> %tmp4
|
||||
%tmp4 = call <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8> %tmp2, <16 x i8> %tmp3)
|
||||
%tmp5 = add <16 x i8> %tmp1, %tmp4
|
||||
ret <16 x i8> %tmp5
|
||||
}
|
||||
|
||||
define <8 x i16> @vabaQu16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
|
||||
|
|
@ -106,8 +116,9 @@ define <8 x i16> @vabaQu16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind
|
|||
%tmp1 = load <8 x i16>* %A
|
||||
%tmp2 = load <8 x i16>* %B
|
||||
%tmp3 = load <8 x i16>* %C
|
||||
%tmp4 = call <8 x i16> @llvm.arm.neon.vabau.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> %tmp3)
|
||||
ret <8 x i16> %tmp4
|
||||
%tmp4 = call <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp3)
|
||||
%tmp5 = add <8 x i16> %tmp1, %tmp4
|
||||
ret <8 x i16> %tmp5
|
||||
}
|
||||
|
||||
define <4 x i32> @vabaQu32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
|
||||
|
|
@ -116,25 +127,26 @@ define <4 x i32> @vabaQu32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind
|
|||
%tmp1 = load <4 x i32>* %A
|
||||
%tmp2 = load <4 x i32>* %B
|
||||
%tmp3 = load <4 x i32>* %C
|
||||
%tmp4 = call <4 x i32> @llvm.arm.neon.vabau.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> %tmp3)
|
||||
ret <4 x i32> %tmp4
|
||||
%tmp4 = call <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32> %tmp2, <4 x i32> %tmp3)
|
||||
%tmp5 = add <4 x i32> %tmp1, %tmp4
|
||||
ret <4 x i32> %tmp5
|
||||
}
|
||||
|
||||
declare <8 x i8> @llvm.arm.neon.vabas.v8i8(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
|
||||
declare <4 x i16> @llvm.arm.neon.vabas.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) nounwind readnone
|
||||
declare <2 x i32> @llvm.arm.neon.vabas.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) nounwind readnone
|
||||
declare <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
|
||||
declare <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
|
||||
declare <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
|
||||
|
||||
declare <8 x i8> @llvm.arm.neon.vabau.v8i8(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
|
||||
declare <4 x i16> @llvm.arm.neon.vabau.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) nounwind readnone
|
||||
declare <2 x i32> @llvm.arm.neon.vabau.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) nounwind readnone
|
||||
declare <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
|
||||
declare <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
|
||||
declare <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
|
||||
|
||||
declare <16 x i8> @llvm.arm.neon.vabas.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
|
||||
declare <8 x i16> @llvm.arm.neon.vabas.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone
|
||||
declare <4 x i32> @llvm.arm.neon.vabas.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
|
||||
declare <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
|
||||
declare <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
|
||||
declare <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
|
||||
|
||||
declare <16 x i8> @llvm.arm.neon.vabau.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
|
||||
declare <8 x i16> @llvm.arm.neon.vabau.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone
|
||||
declare <4 x i32> @llvm.arm.neon.vabau.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
|
||||
declare <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
|
||||
declare <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
|
||||
declare <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
|
||||
|
||||
define <8 x i16> @vabals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
|
||||
;CHECK: vabals8:
|
||||
|
|
@ -142,8 +154,10 @@ define <8 x i16> @vabals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
|
|||
%tmp1 = load <8 x i16>* %A
|
||||
%tmp2 = load <8 x i8>* %B
|
||||
%tmp3 = load <8 x i8>* %C
|
||||
%tmp4 = call <8 x i16> @llvm.arm.neon.vabals.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3)
|
||||
ret <8 x i16> %tmp4
|
||||
%tmp4 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3)
|
||||
%tmp5 = zext <8 x i8> %tmp4 to <8 x i16>
|
||||
%tmp6 = add <8 x i16> %tmp1, %tmp5
|
||||
ret <8 x i16> %tmp6
|
||||
}
|
||||
|
||||
define <4 x i32> @vabals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
|
||||
|
|
@ -152,8 +166,10 @@ define <4 x i32> @vabals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
|
|||
%tmp1 = load <4 x i32>* %A
|
||||
%tmp2 = load <4 x i16>* %B
|
||||
%tmp3 = load <4 x i16>* %C
|
||||
%tmp4 = call <4 x i32> @llvm.arm.neon.vabals.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3)
|
||||
ret <4 x i32> %tmp4
|
||||
%tmp4 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3)
|
||||
%tmp5 = zext <4 x i16> %tmp4 to <4 x i32>
|
||||
%tmp6 = add <4 x i32> %tmp1, %tmp5
|
||||
ret <4 x i32> %tmp6
|
||||
}
|
||||
|
||||
define <2 x i64> @vabals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
|
||||
|
|
@ -162,8 +178,10 @@ define <2 x i64> @vabals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
|
|||
%tmp1 = load <2 x i64>* %A
|
||||
%tmp2 = load <2 x i32>* %B
|
||||
%tmp3 = load <2 x i32>* %C
|
||||
%tmp4 = call <2 x i64> @llvm.arm.neon.vabals.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3)
|
||||
ret <2 x i64> %tmp4
|
||||
%tmp4 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3)
|
||||
%tmp5 = zext <2 x i32> %tmp4 to <2 x i64>
|
||||
%tmp6 = add <2 x i64> %tmp1, %tmp5
|
||||
ret <2 x i64> %tmp6
|
||||
}
|
||||
|
||||
define <8 x i16> @vabalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
|
||||
|
|
@ -172,8 +190,10 @@ define <8 x i16> @vabalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
|
|||
%tmp1 = load <8 x i16>* %A
|
||||
%tmp2 = load <8 x i8>* %B
|
||||
%tmp3 = load <8 x i8>* %C
|
||||
%tmp4 = call <8 x i16> @llvm.arm.neon.vabalu.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3)
|
||||
ret <8 x i16> %tmp4
|
||||
%tmp4 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3)
|
||||
%tmp5 = zext <8 x i8> %tmp4 to <8 x i16>
|
||||
%tmp6 = add <8 x i16> %tmp1, %tmp5
|
||||
ret <8 x i16> %tmp6
|
||||
}
|
||||
|
||||
define <4 x i32> @vabalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
|
||||
|
|
@ -182,8 +202,10 @@ define <4 x i32> @vabalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
|
|||
%tmp1 = load <4 x i32>* %A
|
||||
%tmp2 = load <4 x i16>* %B
|
||||
%tmp3 = load <4 x i16>* %C
|
||||
%tmp4 = call <4 x i32> @llvm.arm.neon.vabalu.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3)
|
||||
ret <4 x i32> %tmp4
|
||||
%tmp4 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3)
|
||||
%tmp5 = zext <4 x i16> %tmp4 to <4 x i32>
|
||||
%tmp6 = add <4 x i32> %tmp1, %tmp5
|
||||
ret <4 x i32> %tmp6
|
||||
}
|
||||
|
||||
define <2 x i64> @vabalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
|
||||
|
|
@ -192,38 +214,8 @@ define <2 x i64> @vabalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
|
|||
%tmp1 = load <2 x i64>* %A
|
||||
%tmp2 = load <2 x i32>* %B
|
||||
%tmp3 = load <2 x i32>* %C
|
||||
%tmp4 = call <2 x i64> @llvm.arm.neon.vabalu.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3)
|
||||
ret <2 x i64> %tmp4
|
||||
%tmp4 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3)
|
||||
%tmp5 = zext <2 x i32> %tmp4 to <2 x i64>
|
||||
%tmp6 = add <2 x i64> %tmp1, %tmp5
|
||||
ret <2 x i64> %tmp6
|
||||
}
|
||||
|
||||
declare <8 x i16> @llvm.arm.neon.vabals.v8i16(<8 x i16>, <8 x i8>, <8 x i8>) nounwind readnone
|
||||
declare <4 x i32> @llvm.arm.neon.vabals.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone
|
||||
declare <2 x i64> @llvm.arm.neon.vabals.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone
|
||||
|
||||
declare <8 x i16> @llvm.arm.neon.vabalu.v8i16(<8 x i16>, <8 x i8>, <8 x i8>) nounwind readnone
|
||||
declare <4 x i32> @llvm.arm.neon.vabalu.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone
|
||||
declare <2 x i64> @llvm.arm.neon.vabalu.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone
|
||||
|
||||
define <8 x i8> @vabd_combine_s8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
;CHECK: vabd_combine_s8:
|
||||
;CHECK: vaba.s8
|
||||
%tmp1 = load <8 x i8>* %A
|
||||
%tmp2 = load <8 x i8>* %B
|
||||
%tmp3 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
|
||||
%tmp4 = add <8 x i8> %tmp2, %tmp3
|
||||
ret <8 x i8> %tmp4
|
||||
}
|
||||
|
||||
define <4 x i16> @vabd_combine_u16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
||||
;CHECK: vabd_combine_u16:
|
||||
;CHECK: vaba.u16
|
||||
%tmp1 = load <4 x i16>* %A
|
||||
%tmp2 = load <4 x i16>* %B
|
||||
%tmp3 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
|
||||
%tmp4 = add <4 x i16> %tmp3, %tmp1
|
||||
ret <4 x i16> %tmp4
|
||||
}
|
||||
|
||||
declare <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
|
||||
declare <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
|
||||
|
||||
|
|
|
|||
|
|
@ -151,8 +151,9 @@ define <8 x i16> @vabdls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
|||
;CHECK: vabdl.s8
|
||||
%tmp1 = load <8 x i8>* %A
|
||||
%tmp2 = load <8 x i8>* %B
|
||||
%tmp3 = call <8 x i16> @llvm.arm.neon.vabdls.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
|
||||
ret <8 x i16> %tmp3
|
||||
%tmp3 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
|
||||
%tmp4 = zext <8 x i8> %tmp3 to <8 x i16>
|
||||
ret <8 x i16> %tmp4
|
||||
}
|
||||
|
||||
define <4 x i32> @vabdls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
||||
|
|
@ -160,8 +161,9 @@ define <4 x i32> @vabdls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
|||
;CHECK: vabdl.s16
|
||||
%tmp1 = load <4 x i16>* %A
|
||||
%tmp2 = load <4 x i16>* %B
|
||||
%tmp3 = call <4 x i32> @llvm.arm.neon.vabdls.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
|
||||
ret <4 x i32> %tmp3
|
||||
%tmp3 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
|
||||
%tmp4 = zext <4 x i16> %tmp3 to <4 x i32>
|
||||
ret <4 x i32> %tmp4
|
||||
}
|
||||
|
||||
define <2 x i64> @vabdls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
|
||||
|
|
@ -169,8 +171,9 @@ define <2 x i64> @vabdls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
|
|||
;CHECK: vabdl.s32
|
||||
%tmp1 = load <2 x i32>* %A
|
||||
%tmp2 = load <2 x i32>* %B
|
||||
%tmp3 = call <2 x i64> @llvm.arm.neon.vabdls.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
|
||||
ret <2 x i64> %tmp3
|
||||
%tmp3 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
|
||||
%tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
|
||||
ret <2 x i64> %tmp4
|
||||
}
|
||||
|
||||
define <8 x i16> @vabdlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
|
|
@ -178,8 +181,9 @@ define <8 x i16> @vabdlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
|||
;CHECK: vabdl.u8
|
||||
%tmp1 = load <8 x i8>* %A
|
||||
%tmp2 = load <8 x i8>* %B
|
||||
%tmp3 = call <8 x i16> @llvm.arm.neon.vabdlu.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
|
||||
ret <8 x i16> %tmp3
|
||||
%tmp3 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
|
||||
%tmp4 = zext <8 x i8> %tmp3 to <8 x i16>
|
||||
ret <8 x i16> %tmp4
|
||||
}
|
||||
|
||||
define <4 x i32> @vabdlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
||||
|
|
@ -187,8 +191,9 @@ define <4 x i32> @vabdlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
|||
;CHECK: vabdl.u16
|
||||
%tmp1 = load <4 x i16>* %A
|
||||
%tmp2 = load <4 x i16>* %B
|
||||
%tmp3 = call <4 x i32> @llvm.arm.neon.vabdlu.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
|
||||
ret <4 x i32> %tmp3
|
||||
%tmp3 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
|
||||
%tmp4 = zext <4 x i16> %tmp3 to <4 x i32>
|
||||
ret <4 x i32> %tmp4
|
||||
}
|
||||
|
||||
define <2 x i64> @vabdlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
|
||||
|
|
@ -196,14 +201,7 @@ define <2 x i64> @vabdlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
|
|||
;CHECK: vabdl.u32
|
||||
%tmp1 = load <2 x i32>* %A
|
||||
%tmp2 = load <2 x i32>* %B
|
||||
%tmp3 = call <2 x i64> @llvm.arm.neon.vabdlu.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
|
||||
ret <2 x i64> %tmp3
|
||||
%tmp3 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
|
||||
%tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
|
||||
ret <2 x i64> %tmp4
|
||||
}
|
||||
|
||||
declare <8 x i16> @llvm.arm.neon.vabdls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
|
||||
declare <4 x i32> @llvm.arm.neon.vabdls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
|
||||
declare <2 x i64> @llvm.arm.neon.vabdls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
|
||||
|
||||
declare <8 x i16> @llvm.arm.neon.vabdlu.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
|
||||
declare <4 x i32> @llvm.arm.neon.vabdlu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
|
||||
declare <2 x i64> @llvm.arm.neon.vabdlu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
|
||||
|
|
|
|||
Loading…
Reference in New Issue