forked from OSchip/llvm-project
AMDGPU: Add encodings for global atomics
llvm-svn: 308638
This commit is contained in:
Matt Arsenault
parent
bedb2601c1
commit
f65c5ac9c9
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@ -181,46 +181,94 @@ class FLAT_Scratch_Store_Pseudo<string opName, RegisterClass regClass> :
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let is_flat_scratch = 1;
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let is_flat_scratch = 1;
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}
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}
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class FLAT_AtomicNoRet_Pseudo<string opName, dag outs, dag ins,
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string asm, list<dag> pattern = []> :
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FLAT_Pseudo<opName, outs, ins, asm, pattern> {
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let mayLoad = 1;
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let mayStore = 1;
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let has_glc = 0;
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let glcValue = 0;
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let has_vdst = 0;
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}
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class FLAT_AtomicRet_Pseudo<string opName, dag outs, dag ins,
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string asm, list<dag> pattern = []>
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: FLAT_AtomicNoRet_Pseudo<opName, outs, ins, asm, pattern> {
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let hasPostISelHook = 1;
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let has_vdst = 1;
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let glcValue = 1;
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let PseudoInstr = NAME # "_RTN";
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}
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multiclass FLAT_Atomic_Pseudo<
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multiclass FLAT_Atomic_Pseudo<
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string opName,
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string opName,
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RegisterClass vdst_rc,
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RegisterClass vdst_rc,
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ValueType vt,
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ValueType vt,
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SDPatternOperator atomic = null_frag,
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SDPatternOperator atomic = null_frag,
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ValueType data_vt = vt,
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ValueType data_vt = vt,
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RegisterClass data_rc = vdst_rc,
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RegisterClass data_rc = vdst_rc> {
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bit HasSignedOffset = 0> {
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def "" : FLAT_AtomicNoRet_Pseudo <opName,
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def "" : FLAT_Pseudo <opName,
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(outs),
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(outs),
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!if(HasSignedOffset,
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(ins VReg_64:$vaddr, data_rc:$vdata, offset_u12:$offset, slc:$slc),
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(ins VReg_64:$vaddr, data_rc:$vdata, offset_s13:$offset, slc:$slc),
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" $vaddr, $vdata$offset$slc">,
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(ins VReg_64:$vaddr, data_rc:$vdata, offset_u12:$offset, slc:$slc)),
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AtomicNoRet <opName, 0> {
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" $vaddr, $vdata$offset$slc",
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[]>,
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AtomicNoRet <NAME, 0> {
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let mayLoad = 1;
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let mayStore = 1;
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let has_glc = 0;
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let glcValue = 0;
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let has_vdst = 0;
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let PseudoInstr = NAME;
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let PseudoInstr = NAME;
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}
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}
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def _RTN : FLAT_Pseudo <opName,
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def _RTN : FLAT_AtomicRet_Pseudo <opName,
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(outs vdst_rc:$vdst),
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(outs vdst_rc:$vdst),
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!if(HasSignedOffset,
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(ins VReg_64:$vaddr, data_rc:$vdata, offset_u12:$offset, slc:$slc),
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(ins VReg_64:$vaddr, data_rc:$vdata, offset_s13:$offset, slc:$slc),
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(ins VReg_64:$vaddr, data_rc:$vdata, offset_u12:$offset, slc:$slc)),
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" $vdst, $vaddr, $vdata$offset glc$slc",
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" $vdst, $vaddr, $vdata$offset glc$slc",
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[(set vt:$vdst,
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[(set vt:$vdst,
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(atomic (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$vdata))]>,
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(atomic (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$vdata))]>,
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AtomicNoRet <NAME, 1> {
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AtomicNoRet <opName, 1>;
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let mayLoad = 1;
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}
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let mayStore = 1;
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let hasPostISelHook = 1;
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multiclass FLAT_Global_Atomic_Pseudo<
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let has_glc = 0;
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string opName,
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let glcValue = 1;
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RegisterClass vdst_rc,
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let PseudoInstr = NAME # "_RTN";
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ValueType vt,
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SDPatternOperator atomic = null_frag,
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ValueType data_vt = vt,
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RegisterClass data_rc = vdst_rc> {
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def "" : FLAT_AtomicNoRet_Pseudo <opName,
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(outs),
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(ins VReg_64:$vaddr, data_rc:$vdata, offset_s13:$offset, slc:$slc),
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" $vaddr, $vdata, off$offset$slc">,
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AtomicNoRet <opName, 0> {
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let has_saddr = 1;
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let PseudoInstr = NAME;
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}
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def _RTN : FLAT_AtomicRet_Pseudo <opName,
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(outs vdst_rc:$vdst),
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(ins VReg_64:$vaddr, data_rc:$vdata, offset_s13:$offset, slc:$slc),
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" $vdst, $vaddr, $vdata, off$offset glc$slc",
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[(set vt:$vdst,
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(atomic (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$vdata))]>,
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AtomicNoRet <opName, 1> {
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let has_saddr = 1;
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}
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def _SADDR : FLAT_AtomicNoRet_Pseudo <opName,
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(outs),
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(ins VReg_64:$vaddr, data_rc:$vdata, SReg_64:$saddr, offset_s13:$offset, slc:$slc),
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" $vaddr, $vdata$saddr$offset$slc">,
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AtomicNoRet <opName#"_saddr", 0> {
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let has_saddr = 1;
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let enabled_saddr = 1;
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let PseudoInstr = NAME#"_SADDR";
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}
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def _SADDR_RTN : FLAT_AtomicRet_Pseudo <opName,
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(outs vdst_rc:$vdst),
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(ins VReg_64:$vaddr, data_rc:$vdata, SReg_64:$saddr, offset_s13:$offset, slc:$slc),
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" $vdst, $vaddr, $vdata$saddr$offset glc$slc">,
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AtomicNoRet <opName#"_saddr", 1> {
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let has_saddr = 1;
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let enabled_saddr = 1;
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let PseudoInstr = NAME#"_SADDR_RTN";
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}
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}
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}
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}
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@ -385,6 +433,89 @@ defm GLOBAL_STORE_DWORDX2 : FLAT_Global_Store_Pseudo <"global_store_dwordx2", VR
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defm GLOBAL_STORE_DWORDX3 : FLAT_Global_Store_Pseudo <"global_store_dwordx3", VReg_96>;
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defm GLOBAL_STORE_DWORDX3 : FLAT_Global_Store_Pseudo <"global_store_dwordx3", VReg_96>;
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defm GLOBAL_STORE_DWORDX4 : FLAT_Global_Store_Pseudo <"global_store_dwordx4", VReg_128>;
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defm GLOBAL_STORE_DWORDX4 : FLAT_Global_Store_Pseudo <"global_store_dwordx4", VReg_128>;
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let is_flat_global = 1 in {
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defm GLOBAL_ATOMIC_CMPSWAP : FLAT_Global_Atomic_Pseudo <"global_atomic_cmpswap",
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VGPR_32, i32, AMDGPUatomic_cmp_swap_global,
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v2i32, VReg_64>;
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defm GLOBAL_ATOMIC_CMPSWAP_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_cmpswap_x2",
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VReg_64, i64, AMDGPUatomic_cmp_swap_global,
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v2i64, VReg_128>;
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defm GLOBAL_ATOMIC_SWAP : FLAT_Global_Atomic_Pseudo <"global_atomic_swap",
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VGPR_32, i32, atomic_swap_global>;
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defm GLOBAL_ATOMIC_SWAP_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_swap_x2",
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VReg_64, i64, atomic_swap_global>;
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defm GLOBAL_ATOMIC_ADD : FLAT_Global_Atomic_Pseudo <"global_atomic_add",
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VGPR_32, i32, atomic_add_global>;
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defm GLOBAL_ATOMIC_SUB : FLAT_Global_Atomic_Pseudo <"global_atomic_sub",
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VGPR_32, i32, atomic_sub_global>;
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defm GLOBAL_ATOMIC_SMIN : FLAT_Global_Atomic_Pseudo <"global_atomic_smin",
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VGPR_32, i32, atomic_min_global>;
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defm GLOBAL_ATOMIC_UMIN : FLAT_Global_Atomic_Pseudo <"global_atomic_umin",
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VGPR_32, i32, atomic_umin_global>;
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defm GLOBAL_ATOMIC_SMAX : FLAT_Global_Atomic_Pseudo <"global_atomic_smax",
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VGPR_32, i32, atomic_max_global>;
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defm GLOBAL_ATOMIC_UMAX : FLAT_Global_Atomic_Pseudo <"global_atomic_umax",
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VGPR_32, i32, atomic_umax_global>;
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defm GLOBAL_ATOMIC_AND : FLAT_Global_Atomic_Pseudo <"global_atomic_and",
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VGPR_32, i32, atomic_and_global>;
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defm GLOBAL_ATOMIC_OR : FLAT_Global_Atomic_Pseudo <"global_atomic_or",
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VGPR_32, i32, atomic_or_global>;
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defm GLOBAL_ATOMIC_XOR : FLAT_Global_Atomic_Pseudo <"global_atomic_xor",
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VGPR_32, i32, atomic_xor_global>;
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defm GLOBAL_ATOMIC_INC : FLAT_Global_Atomic_Pseudo <"global_atomic_inc",
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VGPR_32, i32, atomic_inc_global>;
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defm GLOBAL_ATOMIC_DEC : FLAT_Global_Atomic_Pseudo <"global_atomic_dec",
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VGPR_32, i32, atomic_dec_global>;
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defm GLOBAL_ATOMIC_ADD_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_add_x2",
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VReg_64, i64, atomic_add_global>;
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defm GLOBAL_ATOMIC_SUB_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_sub_x2",
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VReg_64, i64, atomic_sub_global>;
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defm GLOBAL_ATOMIC_SMIN_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_smin_x2",
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VReg_64, i64, atomic_min_global>;
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defm GLOBAL_ATOMIC_UMIN_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_umin_x2",
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VReg_64, i64, atomic_umin_global>;
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defm GLOBAL_ATOMIC_SMAX_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_smax_x2",
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VReg_64, i64, atomic_max_global>;
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defm GLOBAL_ATOMIC_UMAX_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_umax_x2",
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VReg_64, i64, atomic_umax_global>;
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defm GLOBAL_ATOMIC_AND_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_and_x2",
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VReg_64, i64, atomic_and_global>;
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defm GLOBAL_ATOMIC_OR_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_or_x2",
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VReg_64, i64, atomic_or_global>;
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defm GLOBAL_ATOMIC_XOR_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_xor_x2",
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VReg_64, i64, atomic_xor_global>;
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defm GLOBAL_ATOMIC_INC_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_inc_x2",
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VReg_64, i64, atomic_inc_global>;
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defm GLOBAL_ATOMIC_DEC_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_dec_x2",
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VReg_64, i64, atomic_dec_global>;
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} // End is_flat_global = 1
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} // End SubtargetPredicate = HasFlatGlobalInsts
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} // End SubtargetPredicate = HasFlatGlobalInsts
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@ -617,6 +748,13 @@ multiclass FLAT_Real_Atomics_vi <bits<7> op, FLAT_Pseudo ps> {
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def _RTN_vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(ps.PseudoInstr # "_RTN")>;
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def _RTN_vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(ps.PseudoInstr # "_RTN")>;
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}
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}
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multiclass FLAT_Global_Real_Atomics_vi<bits<7> op> :
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FLAT_Real_AllAddr_vi<op> {
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def _RTN_vi : FLAT_Real_vi <op, !cast<FLAT_Pseudo>(NAME#"_RTN")>;
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def _SADDR_RTN_vi : FLAT_Real_vi <op, !cast<FLAT_Pseudo>(NAME#"_SADDR_RTN")>;
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}
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defm FLAT_ATOMIC_SWAP : FLAT_Real_Atomics_vi <0x40, FLAT_ATOMIC_SWAP>;
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defm FLAT_ATOMIC_SWAP : FLAT_Real_Atomics_vi <0x40, FLAT_ATOMIC_SWAP>;
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defm FLAT_ATOMIC_CMPSWAP : FLAT_Real_Atomics_vi <0x41, FLAT_ATOMIC_CMPSWAP>;
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defm FLAT_ATOMIC_CMPSWAP : FLAT_Real_Atomics_vi <0x41, FLAT_ATOMIC_CMPSWAP>;
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defm FLAT_ATOMIC_ADD : FLAT_Real_Atomics_vi <0x42, FLAT_ATOMIC_ADD>;
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defm FLAT_ATOMIC_ADD : FLAT_Real_Atomics_vi <0x42, FLAT_ATOMIC_ADD>;
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@ -659,3 +797,30 @@ defm GLOBAL_STORE_DWORD : FLAT_Real_AllAddr_vi <0x1c>;
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defm GLOBAL_STORE_DWORDX2 : FLAT_Real_AllAddr_vi <0x1d>;
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defm GLOBAL_STORE_DWORDX2 : FLAT_Real_AllAddr_vi <0x1d>;
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defm GLOBAL_STORE_DWORDX4 : FLAT_Real_AllAddr_vi <0x1f>;
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defm GLOBAL_STORE_DWORDX4 : FLAT_Real_AllAddr_vi <0x1f>;
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defm GLOBAL_STORE_DWORDX3 : FLAT_Real_AllAddr_vi <0x1e>;
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defm GLOBAL_STORE_DWORDX3 : FLAT_Real_AllAddr_vi <0x1e>;
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defm GLOBAL_ATOMIC_SWAP : FLAT_Global_Real_Atomics_vi <0x40>;
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defm GLOBAL_ATOMIC_CMPSWAP : FLAT_Global_Real_Atomics_vi <0x41>;
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defm GLOBAL_ATOMIC_ADD : FLAT_Global_Real_Atomics_vi <0x42>;
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defm GLOBAL_ATOMIC_SUB : FLAT_Global_Real_Atomics_vi <0x43>;
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defm GLOBAL_ATOMIC_SMIN : FLAT_Global_Real_Atomics_vi <0x44>;
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defm GLOBAL_ATOMIC_UMIN : FLAT_Global_Real_Atomics_vi <0x45>;
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defm GLOBAL_ATOMIC_SMAX : FLAT_Global_Real_Atomics_vi <0x46>;
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defm GLOBAL_ATOMIC_UMAX : FLAT_Global_Real_Atomics_vi <0x47>;
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defm GLOBAL_ATOMIC_AND : FLAT_Global_Real_Atomics_vi <0x48>;
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defm GLOBAL_ATOMIC_OR : FLAT_Global_Real_Atomics_vi <0x49>;
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defm GLOBAL_ATOMIC_XOR : FLAT_Global_Real_Atomics_vi <0x4a>;
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defm GLOBAL_ATOMIC_INC : FLAT_Global_Real_Atomics_vi <0x4b>;
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defm GLOBAL_ATOMIC_DEC : FLAT_Global_Real_Atomics_vi <0x4c>;
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defm GLOBAL_ATOMIC_SWAP_X2 : FLAT_Global_Real_Atomics_vi <0x60>;
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defm GLOBAL_ATOMIC_CMPSWAP_X2 : FLAT_Global_Real_Atomics_vi <0x61>;
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defm GLOBAL_ATOMIC_ADD_X2 : FLAT_Global_Real_Atomics_vi <0x62>;
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defm GLOBAL_ATOMIC_SUB_X2 : FLAT_Global_Real_Atomics_vi <0x63>;
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defm GLOBAL_ATOMIC_SMIN_X2 : FLAT_Global_Real_Atomics_vi <0x64>;
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defm GLOBAL_ATOMIC_UMIN_X2 : FLAT_Global_Real_Atomics_vi <0x65>;
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defm GLOBAL_ATOMIC_SMAX_X2 : FLAT_Global_Real_Atomics_vi <0x66>;
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defm GLOBAL_ATOMIC_UMAX_X2 : FLAT_Global_Real_Atomics_vi <0x67>;
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defm GLOBAL_ATOMIC_AND_X2 : FLAT_Global_Real_Atomics_vi <0x68>;
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defm GLOBAL_ATOMIC_OR_X2 : FLAT_Global_Real_Atomics_vi <0x69>;
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defm GLOBAL_ATOMIC_XOR_X2 : FLAT_Global_Real_Atomics_vi <0x6a>;
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defm GLOBAL_ATOMIC_INC_X2 : FLAT_Global_Real_Atomics_vi <0x6b>;
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defm GLOBAL_ATOMIC_DEC_X2 : FLAT_Global_Real_Atomics_vi <0x6c>;
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@ -33,6 +33,7 @@ global_load_dwordx3 v[1:3], v[3:4], off
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global_load_dwordx4 v[1:4], v[3:4], off
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global_load_dwordx4 v[1:4], v[3:4], off
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// GFX9: global_load_dwordx4 v[1:4], v[3:4], off ; encoding: [0x00,0x80,0x5c,0xdc,0x03,0x00,0x7f,0x01]
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// GFX9: global_load_dwordx4 v[1:4], v[3:4], off ; encoding: [0x00,0x80,0x5c,0xdc,0x03,0x00,0x7f,0x01]
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// VI-ERR: instruction not supported on this GPU
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// VI-ERR: instruction not supported on this GPU
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// FIXME: VI error should be instruction nto supported
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// FIXME: VI error should be instruction nto supported
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global_load_dword v1, v[3:4], off offset:0
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global_load_dword v1, v[3:4], off offset:0
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// GFX9: global_load_dword v1, v[3:4], off ; encoding: [0x00,0x80,0x50,0xdc,0x03,0x00,0x7f,0x01]
|
// GFX9: global_load_dword v1, v[3:4], off ; encoding: [0x00,0x80,0x50,0xdc,0x03,0x00,0x7f,0x01]
|
||||||
|
|
@ -122,3 +123,211 @@ global_load_dword v1, v[3:4], s2
|
||||||
global_load_dword v1, v[3:4], exec_hi
|
global_load_dword v1, v[3:4], exec_hi
|
||||||
// GFX9-ERR: :31: error: invalid operand for instruction
|
// GFX9-ERR: :31: error: invalid operand for instruction
|
||||||
// VI-ERR: :31: error: invalid operand for instruction
|
// VI-ERR: :31: error: invalid operand for instruction
|
||||||
|
|
||||||
|
global_atomic_cmpswap v[3:4], v[5:6], off
|
||||||
|
// GFX9: global_atomic_cmpswap v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x04,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: error: instruction not supported on this GPU
|
||||||
|
|
||||||
|
global_atomic_cmpswap_x2 v[3:4], v[5:8], off
|
||||||
|
// GFX9: global_atomic_cmpswap_x2 v[3:4], v[5:8], off ; encoding: [0x00,0x80,0x84,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: error: instruction not supported on this GPU
|
||||||
|
|
||||||
|
global_atomic_swap v[3:4], v5, off
|
||||||
|
// GFX9: global_atomic_swap v[3:4], v5, off ; encoding: [0x00,0x80,0x00,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: error: instruction not supported on this GPU
|
||||||
|
|
||||||
|
global_atomic_swap_x2 v[3:4], v[5:6], off
|
||||||
|
// GFX9: global_atomic_swap_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x80,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: error: instruction not supported on this GPU
|
||||||
|
|
||||||
|
global_atomic_add v[3:4], v5, off
|
||||||
|
// GFX9: global_atomic_add v[3:4], v5, off ; encoding: [0x00,0x80,0x08,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: instruction not supported on this GPU
|
||||||
|
|
||||||
|
global_atomic_sub v[3:4], v5, off
|
||||||
|
// GFX9: global_atomic_sub v[3:4], v5, off ; encoding: [0x00,0x80,0x0c,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: instruction not supported on this GPU
|
||||||
|
|
||||||
|
global_atomic_smin v[3:4], v5, off
|
||||||
|
// GFX9: global_atomic_smin v[3:4], v5, off ; encoding: [0x00,0x80,0x10,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: instruction not supported on this GPU
|
||||||
|
|
||||||
|
global_atomic_umin v[3:4], v5, off
|
||||||
|
// GFX9: global_atomic_umin v[3:4], v5, off ; encoding: [0x00,0x80,0x14,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: instruction not supported on this GPU
|
||||||
|
|
||||||
|
global_atomic_smax v[3:4], v5, off
|
||||||
|
// GFX9: global_atomic_smax v[3:4], v5, off ; encoding: [0x00,0x80,0x18,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: instruction not supported on this GPU
|
||||||
|
|
||||||
|
global_atomic_umax v[3:4], v5, off
|
||||||
|
// GFX9: global_atomic_umax v[3:4], v5, off ; encoding: [0x00,0x80,0x1c,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: instruction not supported on this GPU
|
||||||
|
|
||||||
|
global_atomic_and v[3:4], v5, off
|
||||||
|
// GFX9: global_atomic_and v[3:4], v5, off ; encoding: [0x00,0x80,0x20,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: instruction not supported on this GPU
|
||||||
|
|
||||||
|
global_atomic_or v[3:4], v5, off
|
||||||
|
// GFX9: global_atomic_or v[3:4], v5, off ; encoding: [0x00,0x80,0x24,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: instruction not supported on this GPU
|
||||||
|
|
||||||
|
global_atomic_xor v[3:4], v5, off
|
||||||
|
// GFX9: global_atomic_xor v[3:4], v5, off ; encoding: [0x00,0x80,0x28,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: instruction not supported on this GPU
|
||||||
|
|
||||||
|
global_atomic_inc v[3:4], v5, off
|
||||||
|
// GFX9: global_atomic_inc v[3:4], v5, off ; encoding: [0x00,0x80,0x2c,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: instruction not supported on this GPU
|
||||||
|
|
||||||
|
global_atomic_dec v[3:4], v5, off
|
||||||
|
// GFX9: global_atomic_dec v[3:4], v5, off ; encoding: [0x00,0x80,0x30,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: instruction not supported on this GPU
|
||||||
|
|
||||||
|
global_atomic_add_x2 v[3:4], v[5:6], off
|
||||||
|
// GFX9: global_atomic_add_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x88,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: instruction not supported on this GPU
|
||||||
|
|
||||||
|
global_atomic_sub_x2 v[3:4], v[5:6], off
|
||||||
|
// GFX9: global_atomic_sub_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x8c,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: instruction not supported on this GPU
|
||||||
|
|
||||||
|
global_atomic_smin_x2 v[3:4], v[5:6], off
|
||||||
|
// GFX9: global_atomic_smin_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x90,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: instruction not supported on this GPU
|
||||||
|
|
||||||
|
global_atomic_umin_x2 v[3:4], v[5:6], off
|
||||||
|
// GFX9: global_atomic_umin_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x94,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: instruction not supported on this GPU
|
||||||
|
|
||||||
|
global_atomic_smax_x2 v[3:4], v[5:6], off
|
||||||
|
// GFX9: global_atomic_smax_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x98,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: instruction not supported on this GPU
|
||||||
|
|
||||||
|
global_atomic_umax_x2 v[3:4], v[5:6], off
|
||||||
|
// GFX9: global_atomic_umax_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x9c,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: instruction not supported on this GPU
|
||||||
|
|
||||||
|
global_atomic_and_x2 v[3:4], v[5:6], off
|
||||||
|
// GFX9: global_atomic_and_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0xa0,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: instruction not supported on this GPU
|
||||||
|
|
||||||
|
global_atomic_or_x2 v[3:4], v[5:6], off
|
||||||
|
// GFX9: global_atomic_or_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0xa4,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: instruction not supported on this GPU
|
||||||
|
|
||||||
|
global_atomic_xor_x2 v[3:4], v[5:6], off
|
||||||
|
// GFX9: global_atomic_xor_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0xa8,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: instruction not supported on this GPU
|
||||||
|
|
||||||
|
global_atomic_inc_x2 v[3:4], v[5:6], off
|
||||||
|
// GFX9: global_atomic_inc_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0xac,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: instruction not supported on this GPU
|
||||||
|
|
||||||
|
global_atomic_dec_x2 v[3:4], v[5:6], off
|
||||||
|
// GFX9: global_atomic_dec_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0xb0,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: error: instruction not supported on this GPU
|
||||||
|
|
||||||
|
global_atomic_cmpswap v[3:4], v[5:6], off offset:-16
|
||||||
|
// GFX9: global_atomic_cmpswap v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x04,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: :49: error: not a valid operand.
|
||||||
|
|
||||||
|
global_atomic_cmpswap_x2 v[3:4], v[5:8], off offset:-16
|
||||||
|
// GFX9: global_atomic_cmpswap_x2 v[3:4], v[5:8], off offset:-16 ; encoding: [0xf0,0x9f,0x84,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: :52: error: not a valid operand.
|
||||||
|
|
||||||
|
global_atomic_swap v[3:4], v5, off offset:-16
|
||||||
|
// GFX9: global_atomic_swap v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x00,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: :42: error: not a valid operand
|
||||||
|
|
||||||
|
global_atomic_swap_x2 v[3:4], v[5:6], off offset:-16
|
||||||
|
// GFX9: global_atomic_swap_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x80,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: :49: error: not a valid operand
|
||||||
|
|
||||||
|
global_atomic_add v[3:4], v5, off offset:-16
|
||||||
|
// GFX9: global_atomic_add v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x08,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: :41: error: not a valid operand
|
||||||
|
|
||||||
|
global_atomic_sub v[3:4], v5, off offset:-16
|
||||||
|
// GFX9: global_atomic_sub v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x0c,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: :41: error: not a valid operand
|
||||||
|
|
||||||
|
global_atomic_smin v[3:4], v5, off offset:-16
|
||||||
|
// GFX9: global_atomic_smin v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x10,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: :42: error: not a valid operand
|
||||||
|
|
||||||
|
global_atomic_umin v[3:4], v5, off offset:-16
|
||||||
|
// GFX9: global_atomic_umin v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x14,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: :42: error: not a valid operand
|
||||||
|
|
||||||
|
global_atomic_smax v[3:4], v5, off offset:-16
|
||||||
|
// GFX9: global_atomic_smax v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x18,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: :42: error: not a valid operand
|
||||||
|
|
||||||
|
global_atomic_umax v[3:4], v5, off offset:-16
|
||||||
|
// GFX9: global_atomic_umax v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x1c,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: :42: error: not a valid operand
|
||||||
|
|
||||||
|
global_atomic_and v[3:4], v5, off offset:-16
|
||||||
|
// GFX9: global_atomic_and v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x20,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: :41: error: not a valid operand
|
||||||
|
|
||||||
|
global_atomic_or v[3:4], v5, off offset:-16
|
||||||
|
// GFX9: global_atomic_or v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x24,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: :40: error: not a valid operand
|
||||||
|
|
||||||
|
global_atomic_xor v[3:4], v5, off offset:-16
|
||||||
|
// GFX9: global_atomic_xor v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x28,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: :41: error: not a valid operand
|
||||||
|
|
||||||
|
global_atomic_inc v[3:4], v5, off offset:-16
|
||||||
|
// GFX9: global_atomic_inc v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x2c,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: :41: error: not a valid operand
|
||||||
|
|
||||||
|
global_atomic_dec v[3:4], v5, off offset:-16
|
||||||
|
// GFX9: global_atomic_dec v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x30,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: :41: error: not a valid operand
|
||||||
|
|
||||||
|
global_atomic_add_x2 v[3:4], v[5:6], off offset:-16
|
||||||
|
// GFX9: global_atomic_add_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x88,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: :48: error: not a valid operand
|
||||||
|
|
||||||
|
global_atomic_sub_x2 v[3:4], v[5:6], off offset:-16
|
||||||
|
// GFX9: global_atomic_sub_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x8c,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: :48: error: not a valid operand
|
||||||
|
|
||||||
|
global_atomic_smin_x2 v[3:4], v[5:6], off offset:-16
|
||||||
|
// GFX9: global_atomic_smin_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x90,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: :49: error: not a valid operand
|
||||||
|
|
||||||
|
global_atomic_umin_x2 v[3:4], v[5:6], off offset:-16
|
||||||
|
// GFX9: global_atomic_umin_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x94,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: :49: error: not a valid operand
|
||||||
|
|
||||||
|
global_atomic_smax_x2 v[3:4], v[5:6], off offset:-16
|
||||||
|
// GFX9: global_atomic_smax_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x98,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: :49: error: not a valid operand
|
||||||
|
|
||||||
|
global_atomic_umax_x2 v[3:4], v[5:6], off offset:-16
|
||||||
|
// GFX9: global_atomic_umax_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x9c,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: :49: error: not a valid operand
|
||||||
|
|
||||||
|
global_atomic_and_x2 v[3:4], v[5:6], off offset:-16
|
||||||
|
// GFX9: global_atomic_and_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0xa0,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: :48: error: not a valid operand
|
||||||
|
|
||||||
|
global_atomic_or_x2 v[3:4], v[5:6], off offset:-16
|
||||||
|
// GFX9: global_atomic_or_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0xa4,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: :47: error: not a valid operand
|
||||||
|
|
||||||
|
global_atomic_xor_x2 v[3:4], v[5:6], off offset:-16
|
||||||
|
// GFX9: global_atomic_xor_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0xa8,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: :48: error: not a valid operand
|
||||||
|
|
||||||
|
global_atomic_inc_x2 v[3:4], v[5:6], off offset:-16
|
||||||
|
// GFX9: global_atomic_inc_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0xac,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: :48: error: not a valid operand
|
||||||
|
|
||||||
|
global_atomic_dec_x2 v[3:4], v[5:6], off offset:-16
|
||||||
|
// GFX9: global_atomic_dec_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0xb0,0xdd,0x03,0x05,0x7f,0x00]
|
||||||
|
// VI-ERR: :48: error: not a valid operand
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue