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[AVX-512] Remove masked 128/256-bit palignr builtins. We can just use a select in the header file with the older unmasked versions instead. 

llvm-svn: 284920
This commit is contained in:
Craig Topper 2016-10-22 18:32:33 +00:00
parent ae8c2517b4
commit f6373bc6fd
4 changed files with 12 additions and 22 deletions
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2
clang/include/clang/Basic/BuiltinsX86.def
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@ -1961,8 +1961,6 @@ TARGET_BUILTIN(__builtin_ia32_kxnorhi, "UsUsUs","","avx512f")
TARGET_BUILTIN(__builtin_ia32_kxorhi, "UsUsUs","","avx512f")
TARGET_BUILTIN(__builtin_ia32_movntdqa512, "V8LLiV8LLi*","","avx512f")
TARGET_BUILTIN(__builtin_ia32_palignr512_mask, "V64cV64cV64cIiV64cULLi","","avx512bw")
TARGET_BUILTIN(__builtin_ia32_palignr128_mask, "V16cV16cV16cIiV16cUs","","avx512bw,avx512vl")
TARGET_BUILTIN(__builtin_ia32_palignr256_mask, "V32cV32cV32cIiV32cUi","","avx512bw,avx512vl")
TARGET_BUILTIN(__builtin_ia32_dbpsadbw128_mask, "V8sV16cV16cIiV8sUc","","avx512bw,avx512vl")
TARGET_BUILTIN(__builtin_ia32_dbpsadbw256_mask, "V16sV32cV32cIiV16sUs","","avx512bw,avx512vl")
TARGET_BUILTIN(__builtin_ia32_dbpsadbw512_mask, "V32sV64cV64cIiV32sUi","","avx512bw")

2
clang/lib/CodeGen/CGBuiltin.cpp
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@ -7346,8 +7346,6 @@ Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned BuiltinID,
}
case X86::BI__builtin_ia32_palignr128:
case X86::BI__builtin_ia32_palignr256:
case X86::BI__builtin_ia32_palignr128_mask:
case X86::BI__builtin_ia32_palignr256_mask:
case X86::BI__builtin_ia32_palignr512_mask: {
unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[2])->getZExtValue();

28
clang/lib/Headers/avx512vlbwintrin.h
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@ -3313,28 +3313,24 @@ _mm256_mask_permutexvar_epi16 (__m256i __W, __mmask16 __M, __m256i __A,
}
#define _mm_mask_alignr_epi8(W, U, A, B, N) __extension__ ({ \
(__m128i)__builtin_ia32_palignr128_mask((__v16qi)(__m128i)(A), \
(__v16qi)(__m128i)(B), (int)(N), \
(__v16qi)(__m128i)(W), \
(__mmask16)(U)); })
(__m128i)__builtin_ia32_selectb_128((__mmask16)(U), \
_mm_alignr_epi8((A), (B), (int)(N)), \
(__v16qi)(__m128i)(W)); })
#define _mm_maskz_alignr_epi8(U, A, B, N) __extension__ ({ \
(__m128i)__builtin_ia32_palignr128_mask((__v16qi)(__m128i)(A), \
(__v16qi)(__m128i)(B), (int)(N), \
(__v16qi)_mm_setzero_si128(), \
(__mmask16)(U)); })
(__m128i)__builtin_ia32_selectb_128((__mmask16)(U), \
_mm_alignr_epi8((A), (B), (int)(N)), \
(__v16qi)_mm_setzero_si128()); })
#define _mm256_mask_alignr_epi8(W, U, A, B, N) __extension__ ({ \
(__m256i)__builtin_ia32_palignr256_mask((__v32qi)(__m256i)(A), \
(__v32qi)(__m256i)(B), (int)(N), \
(__v32qi)(__m256i)(W), \
(__mmask32)(U)); })
(__m256i)__builtin_ia32_selectb_256((__mmask32)(U), \
_mm256_alignr_epi8((A), (B), (int)(N)), \
(__v32qi)(__m256i)(W)); })
#define _mm256_maskz_alignr_epi8(U, A, B, N) __extension__ ({ \
(__m256i)__builtin_ia32_palignr256_mask((__v32qi)(__m256i)(A), \
(__v32qi)(__m256i)(B), (int)(N), \
(__v32qi)_mm256_setzero_si256(), \
(__mmask32)(U)); })
(__m256i)__builtin_ia32_selectb_256((__mmask32)(U), \
_mm256_alignr_epi8((A), (B), (int)(N)), \
(__v32qi)_mm256_setzero_si256()); })
#define _mm_dbsad_epu8(A, B, imm) __extension__ ({ \
(__m128i)__builtin_ia32_dbpsadbw128_mask((__v16qi)(__m128i)(A), \

2
clang/lib/Sema/SemaChecking.cpp
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@ -2167,8 +2167,6 @@ bool Sema::CheckX86BuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
break;
case X86::BI__builtin_ia32_palignr128:
case X86::BI__builtin_ia32_palignr256:
case X86::BI__builtin_ia32_palignr128_mask:
case X86::BI__builtin_ia32_palignr256_mask:
case X86::BI__builtin_ia32_palignr512_mask:
case X86::BI__builtin_ia32_alignq512_mask:
case X86::BI__builtin_ia32_alignd512_mask: