forked from OSchip/llvm-project
[X86][X87] Tag x87 load/store instructions scheduler classes
llvm-svn: 320192
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@ -423,6 +423,7 @@ def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RST:$op),
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} // SchedRW
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// Floating point loads & stores.
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let SchedRW = [WriteLoad] in {
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let canFoldAsLoad = 1 in {
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def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP,
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[(set RFP32:$dst, (loadf32 addr:$src))]>;
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@ -431,7 +432,7 @@ let isReMaterializable = 1 in
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[(set RFP64:$dst, (loadf64 addr:$src))]>;
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def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP,
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[(set RFP80:$dst, (loadf80 addr:$src))]>;
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}
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} // canFoldAsLoad
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def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP,
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[(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>;
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def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP,
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@ -456,7 +457,9 @@ def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP,
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[(set RFP80:$dst, (X86fild addr:$src, i32))]>;
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def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP,
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[(set RFP80:$dst, (X86fild addr:$src, i64))]>;
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} // SchedRW
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let SchedRW = [WriteStore] in {
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def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP,
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[(store RFP32:$src, addr:$op)]>;
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def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP,
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@ -475,9 +478,11 @@ def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>;
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def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>;
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def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>;
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def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>;
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}
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} // mayStore
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def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP,
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[(store RFP80:$src, addr:$op)]>;
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let mayStore = 1, hasSideEffects = 0 in {
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def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>;
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def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>;
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@ -488,7 +493,8 @@ def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>;
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def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>;
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def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>;
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def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>;
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}
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} // mayStore
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} // SchedRW
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let mayLoad = 1, SchedRW = [WriteLoad] in {
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def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src",
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@ -528,7 +534,7 @@ def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst",
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}
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// FISTTP requires SSE3 even though it's a FPStack op.
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let Predicates = [HasSSE3] in {
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let Predicates = [HasSSE3], SchedRW = [WriteStore] in {
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def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP,
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[(X86fp_to_i16mem RFP32:$src, addr:$op)]>;
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def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP,
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@ -567,7 +573,7 @@ def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RST:$op), "fxch\t$op", IIC_FXCH>;
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}
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// Floating point constant loads.
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let isReMaterializable = 1 in {
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let isReMaterializable = 1, SchedRW = [WriteZero] in {
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def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
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[(set RFP32:$dst, fpimm0)]>;
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def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
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