forked from OSchip/llvm-project
AVX-512: fixed algorithm of building vectors of i1 elements
fixed extract-insert i1 element, load i1, zextload i1 should be with "and $1, %reg" to prevent loading garbage. added a bunch of new tests. llvm-svn: 237793
This commit is contained in:
Elena Demikhovsky
parent
69c6008e49
commit
f61727d880
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@ -1471,6 +1471,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
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setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
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setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
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setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
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setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
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for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
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const MVT VT = (MVT::SimpleValueType)i;
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@ -1500,6 +1504,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
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setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
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setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
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setOperationAction(ISD::AND, MVT::v8i32, Legal);
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setOperationAction(ISD::OR, MVT::v8i32, Legal);
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@ -5188,12 +5194,27 @@ static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
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return NV;
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}
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static SDValue ConvertI1VectorToInterger(SDValue Op, SelectionDAG &DAG) {
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assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
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Op.getScalarValueSizeInBits() == 1 &&
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"Can not convert non-constant vector");
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uint64_t Immediate = 0;
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for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
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SDValue In = Op.getOperand(idx);
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if (In.getOpcode() != ISD::UNDEF)
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Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
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}
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SDLoc dl(Op);
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MVT VT =
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MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
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return DAG.getConstant(Immediate, dl, VT);
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}
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// Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
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SDValue
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X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
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MVT VT = Op.getSimpleValueType();
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assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
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assert((VT.getVectorElementType() == MVT::i1) &&
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"Unexpected type in LowerBUILD_VECTORvXi1!");
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SDLoc dl(Op);
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@ -5209,62 +5230,69 @@ X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
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return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
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}
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bool AllContants = true;
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if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
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SDValue Imm = ConvertI1VectorToInterger(Op, DAG);
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if (Imm.getValueSizeInBits() == VT.getSizeInBits())
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return DAG.getNode(ISD::BITCAST, dl, VT, Imm);
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SDValue ExtVec = DAG.getNode(ISD::BITCAST, dl, MVT::v8i1, Imm);
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return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
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DAG.getIntPtrConstant(0, dl));
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}
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// Vector has one or more non-const elements
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uint64_t Immediate = 0;
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int NonConstIdx = -1;
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SmallVector<unsigned, 16> NonConstIdx;
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bool IsSplat = true;
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unsigned NumNonConsts = 0;
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unsigned NumConsts = 0;
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bool HasConstElts = false;
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int SplatIdx = -1;
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for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
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SDValue In = Op.getOperand(idx);
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if (In.getOpcode() == ISD::UNDEF)
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continue;
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if (!isa<ConstantSDNode>(In)) {
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AllContants = false;
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NonConstIdx = idx;
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NumNonConsts++;
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} else {
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NumConsts++;
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if (cast<ConstantSDNode>(In)->getZExtValue())
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Immediate |= (1ULL << idx);
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if (!isa<ConstantSDNode>(In))
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NonConstIdx.push_back(idx);
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else {
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Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
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HasConstElts = true;
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}
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if (In != Op.getOperand(0))
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if (SplatIdx == -1)
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SplatIdx = idx;
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else if (In != Op.getOperand(SplatIdx))
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IsSplat = false;
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}
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if (AllContants) {
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SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
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DAG.getConstant(Immediate, dl, MVT::i16));
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return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
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DAG.getIntPtrConstant(0, dl));
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// for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
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if (IsSplat)
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return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
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DAG.getConstant(1, dl, VT),
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DAG.getConstant(0, dl, VT));
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// insert elements one by one
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SDValue DstVec;
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SDValue Imm;
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if (Immediate) {
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MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
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Imm = DAG.getConstant(Immediate, dl, ImmVT);
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}
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else if (HasConstElts)
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Imm = DAG.getConstant(0, dl, VT);
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else
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Imm = DAG.getUNDEF(VT);
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if (Imm.getValueSizeInBits() == VT.getSizeInBits())
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DstVec = DAG.getNode(ISD::BITCAST, dl, VT, Imm);
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else {
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SDValue ExtVec = DAG.getNode(ISD::BITCAST, dl, MVT::v8i1, Imm);
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DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
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DAG.getIntPtrConstant(0, dl));
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}
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if (NumNonConsts == 1 && NonConstIdx != 0) {
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SDValue DstVec;
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if (NumConsts) {
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SDValue VecAsImm = DAG.getConstant(Immediate, dl,
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MVT::getIntegerVT(VT.getSizeInBits()));
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DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
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}
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else
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DstVec = DAG.getUNDEF(VT);
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return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
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Op.getOperand(NonConstIdx),
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DAG.getIntPtrConstant(NonConstIdx, dl));
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for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
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unsigned InsertIdx = NonConstIdx[i];
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DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
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Op.getOperand(InsertIdx),
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DAG.getIntPtrConstant(InsertIdx, dl));
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}
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if (!IsSplat && (NonConstIdx != 0))
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llvm_unreachable("Unsupported BUILD_VECTOR operation");
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MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
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SDValue Select;
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if (IsSplat)
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Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
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DAG.getConstant(-1, dl, SelectVT),
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DAG.getConstant(0, dl, SelectVT));
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else
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Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
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DAG.getConstant((Immediate | 1), dl, SelectVT),
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DAG.getConstant(Immediate, dl, SelectVT));
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return DAG.getNode(ISD::BITCAST, dl, VT, Select);
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return DstVec;
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}
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/// \brief Return true if \p N implements a horizontal binop and return the
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@ -10670,15 +10698,11 @@ X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
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unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
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SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
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if (IdxVal)
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EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
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DAG.getConstant(IdxVal, dl, MVT::i8));
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if (Vec.getOpcode() == ISD::UNDEF)
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return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
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DAG.getConstant(IdxVal, dl, MVT::i8));
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const TargetRegisterClass* rc = getRegClassFor(VecVT);
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unsigned MaxSift = rc->getSize()*8 - 1;
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EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
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DAG.getConstant(MaxSift, dl, MVT::i8));
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EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
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DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
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return EltInVec;
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return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
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}
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@ -13623,6 +13647,29 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
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}
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}
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if (VT.isVector() && VT.getScalarType() == MVT::i1) {
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SDValue Op1Scalar;
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if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
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Op1Scalar = ConvertI1VectorToInterger(Op1, DAG);
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else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
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Op1Scalar = Op1.getOperand(0);
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SDValue Op2Scalar;
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if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
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Op2Scalar = ConvertI1VectorToInterger(Op2, DAG);
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else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
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Op2Scalar = Op2.getOperand(0);
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if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
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SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
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Op1Scalar.getValueType(),
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Cond, Op1Scalar, Op2Scalar);
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if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
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return DAG.getNode(ISD::BITCAST, DL, VT, newSelect);
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SDValue ExtVec = DAG.getNode(ISD::BITCAST, DL, MVT::v8i1, newSelect);
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return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
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DAG.getIntPtrConstant(0, DL));
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}
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}
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if (VT == MVT::v4i1 || VT == MVT::v2i1) {
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SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
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Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
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@ -20728,7 +20775,8 @@ static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
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if (!InVec.hasOneUse())
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return SDValue();
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EVT BCVT = InVec.getOperand(0).getValueType();
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if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
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if (!BCVT.isVector() ||
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BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
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return SDValue();
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InVec = InVec.getOperand(0);
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}
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@ -20833,7 +20881,7 @@ static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
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return NewOp;
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SDValue InputVector = N->getOperand(0);
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SDLoc dl(InputVector);
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// Detect mmx to i32 conversion through a v2i32 elt extract.
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if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
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N->getValueType(0) == MVT::i32 &&
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@ -20858,6 +20906,18 @@ static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
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MMXSrcOp.getOperand(0));
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}
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EVT VT = N->getValueType(0);
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if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
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InputVector.getOpcode() == ISD::BITCAST &&
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dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
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uint64_t ExtractedElt =
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cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
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uint64_t InputValue =
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cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
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uint64_t Res = (InputValue >> ExtractedElt) & 1;
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return DAG.getConstant(Res, dl, MVT::i1);
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}
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// Only operate on vectors of 4 elements, where the alternative shuffling
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// gets to be more expensive.
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if (InputVector.getValueType() != MVT::v4i32)
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@ -20903,7 +20963,6 @@ static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
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// otherwise bounce the vector off the cache.
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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SDValue Vals[4];
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SDLoc dl(InputVector);
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if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
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SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
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@ -23606,6 +23665,7 @@ static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget *Subtarget) {
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SDValue N0 = N->getOperand(0);
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EVT VT = N->getValueType(0);
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SDLoc dl(N);
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// (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
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// (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
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@ -23613,7 +23673,6 @@ static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
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// from AH (which we otherwise need to do contortions to access).
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if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
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N0.getValueType() == MVT::i8 && VT == MVT::i32) {
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SDLoc dl(N);
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SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
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SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
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N0.getOperand(0), N0.getOperand(1));
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@ -23621,8 +23680,15 @@ static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
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return R.getValue(1);
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}
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if (!DCI.isBeforeLegalizeOps())
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if (!DCI.isBeforeLegalizeOps()) {
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if (N0.getValueType() == MVT::i1) {
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SDValue Zero = DAG.getConstant(0, dl, VT);
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SDValue AllOnes =
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DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl, VT);
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return DAG.getNode(ISD::SELECT, dl, VT, N0, AllOnes, Zero);
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}
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return SDValue();
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}
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if (!Subtarget->hasFp256())
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return SDValue();
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@ -1855,7 +1855,9 @@ let Predicates = [HasAVX512] in {
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def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
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(KMOVWmk addr:$dst, VK16:$src)>;
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def : Pat<(i1 (load addr:$src)),
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(COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
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(COPY_TO_REGCLASS (AND16ri (i16 (SUBREG_TO_REG (i32 0),
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(MOV8rm addr:$src), sub_8bit)),
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(i16 1)), VK1)>;
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def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
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(KMOVWkm addr:$src)>;
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}
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@ -1920,13 +1922,13 @@ let Predicates = [HasAVX512, NoDQI] in {
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// GR from/to 8-bit mask without native support
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def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
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(COPY_TO_REGCLASS
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(KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
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VK8)>;
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(KMOVWkr (MOVZX32rr8 GR8 :$src)), VK8)>;
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def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
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(EXTRACT_SUBREG
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(KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
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sub_8bit)>;
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}
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let Predicates = [HasAVX512] in {
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def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
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(COPY_TO_REGCLASS VK16:$src, VK1)>;
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@ -1064,11 +1064,12 @@ defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
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defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
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// zextload bool -> zextload byte
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def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
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def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
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def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
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def : Pat<(zextloadi8i1 addr:$src), (AND8ri (MOV8rm addr:$src), (i8 1))>;
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def : Pat<(zextloadi16i1 addr:$src), (AND16ri (MOVZX16rm8 addr:$src), (i16 1))>;
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def : Pat<(zextloadi32i1 addr:$src), (AND32ri (MOVZX32rm8 addr:$src), (i32 1))>;
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def : Pat<(zextloadi64i1 addr:$src),
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(SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
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(SUBREG_TO_REG (i64 0),
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(AND32ri (MOVZX32rm8 addr:$src), (i32 1)), sub_32bit)>;
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// extload bool -> extload byte
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// When extloading from 16-bit and smaller memory locations into 64-bit
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@ -137,10 +137,12 @@ define i64 @test12(<16 x i64>%a, <16 x i64>%b, i64 %a1, i64 %b1) {
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}
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;CHECK-LABEL: test13
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;CHECK: cmpl
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;CHECK: sbbl
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;CHECK: orl $65532
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;CHECK: ret
|
||||
;CHECK: cmpl %esi, %edi
|
||||
;CHECK: setb %al
|
||||
;CHECK: andl $1, %eax
|
||||
;CHECK: kmovw %eax, %k0
|
||||
;CHECK: movw $-4
|
||||
;CHECK: korw
|
||||
define i16 @test13(i32 %a, i32 %b) {
|
||||
%cmp_res = icmp ult i32 %a, %b
|
||||
%maskv = insertelement <16 x i1> <i1 true, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i1 %cmp_res, i32 0
|
||||
|
|
@ -167,19 +169,22 @@ define i64 @test14(<8 x i64>%a, <8 x i64>%b, i64 %a1, i64 %b1) {
|
|||
}
|
||||
|
||||
;CHECK-LABEL: test15
|
||||
;CHECK: kshiftlw
|
||||
;CHECK: kmovw
|
||||
;CHECK: ret
|
||||
;CHECK: movb (%rdi), %al
|
||||
;CHECK: andb $1, %al
|
||||
;CHECK: movw $-1, %ax
|
||||
;CHECK: cmovew
|
||||
define i16 @test15(i1 *%addr) {
|
||||
%x = load i1 , i1 * %addr, align 128
|
||||
%x = load i1 , i1 * %addr, align 1
|
||||
%x1 = insertelement <16 x i1> undef, i1 %x, i32 10
|
||||
%x2 = bitcast <16 x i1>%x1 to i16
|
||||
ret i16 %x2
|
||||
}
|
||||
|
||||
;CHECK-LABEL: test16
|
||||
;CHECK: kshiftlw
|
||||
;CHECK: kshiftrw
|
||||
;CHECK: movb (%rdi), %al
|
||||
;CHECK: andw $1, %ax
|
||||
;CHECK: kmovw
|
||||
;CHECK: kshiftlw $10
|
||||
;CHECK: korw
|
||||
;CHECK: ret
|
||||
define i16 @test16(i1 *%addr, i16 %a) {
|
||||
|
|
@ -191,11 +196,11 @@ define i16 @test16(i1 *%addr, i16 %a) {
|
|||
}
|
||||
|
||||
;CHECK-LABEL: test17
|
||||
;KNL: kshiftlw
|
||||
;KNL: kshiftrw
|
||||
;KNL: movb (%rdi), %al
|
||||
;KNL: andw $1, %ax
|
||||
;KNL: kshiftlw $4
|
||||
;KNL: korw
|
||||
;SKX: kshiftlb
|
||||
;SKX: kshiftrb
|
||||
;SKX: kshiftlb $4
|
||||
;SKX: korb
|
||||
;CHECK: ret
|
||||
define i8 @test17(i1 *%addr, i8 %a) {
|
||||
|
|
|
|||
|
|
@ -191,7 +191,7 @@ false:
|
|||
|
||||
; SKX-LABEL: test7
|
||||
; SKX: vpmovw2m
|
||||
; SKX: kmovw %eax, %k1
|
||||
; SKX: kmovb %eax, %k1
|
||||
; SKX: korb
|
||||
|
||||
define void @test7(<8 x i1> %mask) {
|
||||
|
|
@ -282,3 +282,114 @@ define <4 x i1> @test11(<4 x i1>%a, <4 x i1>%b, i32 %a1, i32 %b1) {
|
|||
ret <4 x i1>%c
|
||||
}
|
||||
|
||||
; KNL-LABEL: test12
|
||||
; KNL: movl %edi, %eax
|
||||
define i32 @test12(i32 %x, i32 %y) {
|
||||
%a = bitcast i16 21845 to <16 x i1>
|
||||
%b = extractelement <16 x i1> %a, i32 0
|
||||
%c = select i1 %b, i32 %x, i32 %y
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
; KNL-LABEL: test13
|
||||
; KNL: movl %esi, %eax
|
||||
define i32 @test13(i32 %x, i32 %y) {
|
||||
%a = bitcast i16 21845 to <16 x i1>
|
||||
%b = extractelement <16 x i1> %a, i32 3
|
||||
%c = select i1 %b, i32 %x, i32 %y
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
; SKX-LABEL: test14
|
||||
; SKX: movb $11, %al
|
||||
; SKX: kmovb %eax, %k0
|
||||
; SKX: vpmovm2d %k0, %xmm0
|
||||
|
||||
define <4 x i1> @test14() {
|
||||
%a = bitcast i16 21845 to <16 x i1>
|
||||
%b = extractelement <16 x i1> %a, i32 2
|
||||
%c = insertelement <4 x i1> <i1 true, i1 false, i1 false, i1 true>, i1 %b, i32 1
|
||||
ret <4 x i1> %c
|
||||
}
|
||||
|
||||
; KNL-LABEL: test15
|
||||
; KNL: cmovgw
|
||||
define <16 x i1> @test15(i32 %x, i32 %y) {
|
||||
%a = bitcast i16 21845 to <16 x i1>
|
||||
%b = bitcast i16 1 to <16 x i1>
|
||||
%mask = icmp sgt i32 %x, %y
|
||||
%c = select i1 %mask, <16 x i1> %a, <16 x i1> %b
|
||||
ret <16 x i1> %c
|
||||
}
|
||||
|
||||
; SKX-LABEL: test16
|
||||
; SKX: kxnorw %k1, %k1, %k1
|
||||
; SKX: kshiftrw $15, %k1, %k1
|
||||
; SKX: kshiftlq $5, %k1, %k1
|
||||
; SKX: korq %k1, %k0, %k0
|
||||
; SKX: vpmovm2b %k0, %zmm0
|
||||
define <64 x i8> @test16(i64 %x) {
|
||||
%a = bitcast i64 %x to <64 x i1>
|
||||
%b = insertelement <64 x i1>%a, i1 true, i32 5
|
||||
%c = sext <64 x i1>%b to <64 x i8>
|
||||
ret <64 x i8>%c
|
||||
}
|
||||
|
||||
; SKX-LABEL: test17
|
||||
; SKX: setg %al
|
||||
; SKX: andl $1, %eax
|
||||
; SKX: kmovw %eax, %k1
|
||||
; SKX: kshiftlq $5, %k1, %k1
|
||||
; SKX: korq %k1, %k0, %k0
|
||||
; SKX: vpmovm2b %k0, %zmm0
|
||||
define <64 x i8> @test17(i64 %x, i32 %y, i32 %z) {
|
||||
%a = bitcast i64 %x to <64 x i1>
|
||||
%b = icmp sgt i32 %y, %z
|
||||
%c = insertelement <64 x i1>%a, i1 %b, i32 5
|
||||
%d = sext <64 x i1>%c to <64 x i8>
|
||||
ret <64 x i8>%d
|
||||
}
|
||||
|
||||
; KNL-LABEL: test18
|
||||
define <8 x i1> @test18(i8 %a, i16 %y) {
|
||||
%b = bitcast i8 %a to <8 x i1>
|
||||
%b1 = bitcast i16 %y to <16 x i1>
|
||||
%el1 = extractelement <16 x i1>%b1, i32 8
|
||||
%el2 = extractelement <16 x i1>%b1, i32 9
|
||||
%c = insertelement <8 x i1>%b, i1 %el1, i32 7
|
||||
%d = insertelement <8 x i1>%c, i1 %el2, i32 6
|
||||
ret <8 x i1>%d
|
||||
}
|
||||
|
||||
; KNL-LABEL: test19
|
||||
; KNL: movzbl %dil, %eax
|
||||
; KNL: kmovw %eax, %k0
|
||||
; KNL: kshiftlw $13, %k0, %k0
|
||||
; KNL: kshiftrw $15, %k0, %k0
|
||||
; KNL: kmovw %k0, %eax
|
||||
; KNL: andl $1, %eax
|
||||
; KNL: testb %al, %al
|
||||
|
||||
define <8 x i1> @test19(i8 %a) {
|
||||
%b = bitcast i8 %a to <8 x i1>
|
||||
%c = shufflevector < 8 x i1>%b, <8 x i1>undef, <8 x i32> <i32 undef, i32 2, i32 undef, i32 undef, i32 2, i32 undef, i32 2, i32 undef>
|
||||
ret <8 x i1> %c
|
||||
}
|
||||
|
||||
; KNL-LABEL: test20
|
||||
; KNL: movzbl %dil, %eax
|
||||
; KNL: kmovw %eax, %k0
|
||||
; KNL: kshiftlw $13, %k0, %k1
|
||||
; KNL: kshiftrw $15, %k1, %k1
|
||||
; KNL: kshiftlw $12, %k0, %k0
|
||||
; KNL: kshiftrw $15, %k0, %k0
|
||||
; KNL: kshiftlw $4, %k0, %k0
|
||||
; KNL: kshiftlw $1, %k1, %k2
|
||||
; KNL: korw %k0, %k2, %k0
|
||||
; KNL: kshiftlw $6, %k1, %k1
|
||||
; KNL: korw %k1, %k0, %k1
|
||||
define <8 x i1> @test20(i8 %a, i16 %y) {
|
||||
%b = bitcast i8 %a to <8 x i1>
|
||||
%c = shufflevector < 8 x i1>%b, <8 x i1>undef, <8 x i32> <i32 undef, i32 2, i32 undef, i32 undef, i32 3, i32 undef, i32 2, i32 undef>
|
||||
ret <8 x i1> %c
|
||||
}
|
||||
|
|
|
|||
|
|
@ -50,8 +50,10 @@ define <16 x double> @select04(<16 x double> %a, <16 x double> %b) {
|
|||
}
|
||||
|
||||
; CHECK-LABEL: select05
|
||||
; CHECK: kmovw %esi, %k0
|
||||
; CHECK-NEXT: kmovw %edi, %k1
|
||||
; CHECK: movzbl %sil, %eax
|
||||
; CHECK: kmovw %eax, %k0
|
||||
; CHECK: movzbl %dil, %eax
|
||||
; CHECK: kmovw %eax, %k1
|
||||
; CHECK-NEXT: korw %k1, %k0, %k0
|
||||
; CHECK-NEXT: kmovw %k0, %eax
|
||||
define i8 @select05(i8 %a.0, i8 %m) {
|
||||
|
|
@ -63,8 +65,10 @@ define i8 @select05(i8 %a.0, i8 %m) {
|
|||
}
|
||||
|
||||
; CHECK-LABEL: select06
|
||||
; CHECK: kmovw %esi, %k0
|
||||
; CHECK-NEXT: kmovw %edi, %k1
|
||||
; CHECK: movzbl %sil, %eax
|
||||
; CHECK: kmovw %eax, %k0
|
||||
; CHECK: movzbl %dil, %eax
|
||||
; CHECK: kmovw %eax, %k1
|
||||
; CHECK-NEXT: kandw %k1, %k0, %k0
|
||||
; CHECK-NEXT: kmovw %k0, %eax
|
||||
define i8 @select06(i8 %a.0, i8 %m) {
|
||||
|
|
@ -76,9 +80,12 @@ define i8 @select06(i8 %a.0, i8 %m) {
|
|||
}
|
||||
|
||||
; CHECK-LABEL: select07
|
||||
; CHECK-DAG: kmovw %edx, %k0
|
||||
; CHECK-DAG: kmovw %edi, %k1
|
||||
; CHECK-DAG: kmovw %esi, %k2
|
||||
; CHECK-DAG: movzbl %dl, %eax
|
||||
; CHECK-DAG: kmovw %eax, %k0
|
||||
; CHECK-DAG: movzbl %dil, %eax
|
||||
; CHECK-DAG: kmovw %eax, %k1
|
||||
; CHECK-DAG: movzbl %sil, %eax
|
||||
; CHECK-DAG: kmovw %eax, %k2
|
||||
; CHECK: kandw %k0, %k1, %k1
|
||||
; CHECK-NEXT: knotw %k0, %k0
|
||||
; CHECK-NEXT: kandw %k0, %k2, %k0
|
||||
|
|
|
|||
|
|
@ -156,10 +156,9 @@ define <16 x i16> @trunc_v16i32_to_v16i16(<16 x i32> %x) {
|
|||
}
|
||||
|
||||
; CHECK-LABEL: trunc_i32_to_i1
|
||||
; CHECK: testb
|
||||
; CHECK: setne
|
||||
; CKECK: orl
|
||||
; CHECK: ret
|
||||
; CHECK: movw $-4, %ax
|
||||
; CHECK: kmovw %eax, %k1
|
||||
; CKECK: korw
|
||||
define i16 @trunc_i32_to_i1(i32 %a) {
|
||||
%a_i = trunc i32 %a to i1
|
||||
%maskv = insertelement <16 x i1> <i1 true, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i1 %a_i, i32 0
|
||||
|
|
|
|||
Loading…
Reference in New Issue