forked from OSchip/llvm-project
[GlobalISel] Implement lowering for G_ROTR and G_ROTL.
This is a straightforward port. Differential Revision: https://reviews.llvm.org/D99449
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Amara Emerson
parent
a9968c0a33
commit
f5e9be6fdb
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@ -348,6 +348,8 @@ public:
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LegalizeResult lowerFunnelShiftWithInverse(MachineInstr &MI);
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LegalizeResult lowerFunnelShiftAsShifts(MachineInstr &MI);
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LegalizeResult lowerFunnelShift(MachineInstr &MI);
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LegalizeResult lowerRotateWithReverseRotate(MachineInstr &MI);
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LegalizeResult lowerRotate(MachineInstr &MI);
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LegalizeResult lowerU64ToF32BitOps(MachineInstr &MI);
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LegalizeResult lowerUITOFP(MachineInstr &MI);
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@ -3228,6 +3228,9 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
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case G_FSHL:
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case G_FSHR:
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return lowerFunnelShift(MI);
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case G_ROTL:
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case G_ROTR:
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return lowerRotate(MI);
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}
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}
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@ -5351,6 +5354,72 @@ LegalizerHelper::lowerFunnelShift(MachineInstr &MI) {
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return lowerFunnelShiftWithInverse(MI);
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::lowerRotateWithReverseRotate(MachineInstr &MI) {
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Register Dst = MI.getOperand(0).getReg();
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Register Src = MI.getOperand(1).getReg();
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Register Amt = MI.getOperand(2).getReg();
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LLT AmtTy = MRI.getType(Amt);
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auto Zero = MIRBuilder.buildConstant(AmtTy, 0);
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bool IsLeft = MI.getOpcode() == TargetOpcode::G_ROTL;
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unsigned RevRot = IsLeft ? TargetOpcode::G_ROTR : TargetOpcode::G_ROTL;
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auto Neg = MIRBuilder.buildSub(AmtTy, Zero, Amt);
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MIRBuilder.buildInstr(RevRot, {Dst}, {Src, Neg});
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MI.eraseFromParent();
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return Legalized;
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}
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LegalizerHelper::LegalizeResult LegalizerHelper::lowerRotate(MachineInstr &MI) {
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Register Dst = MI.getOperand(0).getReg();
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Register Src = MI.getOperand(1).getReg();
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Register Amt = MI.getOperand(2).getReg();
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LLT DstTy = MRI.getType(Dst);
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LLT SrcTy = MRI.getType(Dst);
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LLT AmtTy = MRI.getType(Amt);
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unsigned EltSizeInBits = DstTy.getScalarSizeInBits();
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bool IsLeft = MI.getOpcode() == TargetOpcode::G_ROTL;
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MIRBuilder.setInstrAndDebugLoc(MI);
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// If a rotate in the other direction is supported, use it.
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unsigned RevRot = IsLeft ? TargetOpcode::G_ROTR : TargetOpcode::G_ROTL;
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if (LI.isLegalOrCustom({RevRot, {DstTy, SrcTy}}) &&
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isPowerOf2_32(EltSizeInBits))
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return lowerRotateWithReverseRotate(MI);
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auto Zero = MIRBuilder.buildConstant(AmtTy, 0);
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unsigned ShOpc = IsLeft ? TargetOpcode::G_SHL : TargetOpcode::G_LSHR;
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unsigned RevShiftOpc = IsLeft ? TargetOpcode::G_LSHR : TargetOpcode::G_SHL;
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auto BitWidthMinusOneC = MIRBuilder.buildConstant(AmtTy, EltSizeInBits - 1);
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Register ShVal;
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Register RevShiftVal;
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if (isPowerOf2_32(EltSizeInBits)) {
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// (rotl x, c) -> x << (c & (w - 1)) | x >> (-c & (w - 1))
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// (rotr x, c) -> x >> (c & (w - 1)) | x << (-c & (w - 1))
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auto NegAmt = MIRBuilder.buildSub(AmtTy, Zero, Amt);
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auto ShAmt = MIRBuilder.buildAnd(AmtTy, Amt, BitWidthMinusOneC);
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ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0);
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auto RevAmt = MIRBuilder.buildAnd(AmtTy, NegAmt, BitWidthMinusOneC);
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RevShiftVal =
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MIRBuilder.buildInstr(RevShiftOpc, {DstTy}, {Src, RevAmt}).getReg(0);
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} else {
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// (rotl x, c) -> x << (c % w) | x >> 1 >> (w - 1 - (c % w))
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// (rotr x, c) -> x >> (c % w) | x << 1 << (w - 1 - (c % w))
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auto BitWidthC = MIRBuilder.buildConstant(AmtTy, EltSizeInBits);
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auto ShAmt = MIRBuilder.buildURem(AmtTy, Amt, BitWidthC);
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ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0);
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auto RevAmt = MIRBuilder.buildSub(AmtTy, BitWidthMinusOneC, ShAmt);
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auto One = MIRBuilder.buildConstant(AmtTy, 1);
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auto Inner = MIRBuilder.buildInstr(RevShiftOpc, {DstTy}, {Src, One});
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RevShiftVal =
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MIRBuilder.buildInstr(RevShiftOpc, {DstTy}, {Inner, RevAmt}).getReg(0);
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}
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MIRBuilder.buildOr(Dst, ShVal, RevShiftVal);
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MI.eraseFromParent();
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return Legalized;
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}
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// Expand s32 = G_UITOFP s64 using bit operations to an IEEE float
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// representation.
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LegalizerHelper::LegalizeResult
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@ -23,6 +23,162 @@ public:
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void erasingInstr(MachineInstr &MI) override {}
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};
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// Test G_ROTL/G_ROTR lowering.
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TEST_F(AArch64GISelMITest, LowerRotates) {
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setUp();
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if (!TM)
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return;
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// Declare your legalization info
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DefineLegalizerInfo(A, {
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getActionDefinitionsBuilder({G_ROTR, G_ROTL}).lower(); });
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LLT S32 = LLT::scalar(32);
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auto Src = B.buildTrunc(S32, Copies[0]);
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auto Amt = B.buildTrunc(S32, Copies[1]);
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auto ROTR = B.buildInstr(TargetOpcode::G_ROTR, {S32}, {Src, Amt});
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auto ROTL = B.buildInstr(TargetOpcode::G_ROTL, {S32}, {Src, Amt});
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AInfo Info(MF->getSubtarget());
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DummyGISelObserver Observer;
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LegalizerHelper Helper(*MF, Info, Observer, B);
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// Perform Legalization
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EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,
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Helper.lower(*ROTR, 0, S32));
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EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,
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Helper.lower(*ROTL, 0, S32));
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auto CheckStr = R"(
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; Check G_ROTR
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CHECK: [[SRC:%[0-9]+]]:_(s32) = G_TRUNC
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CHECK: [[AMT:%[0-9]+]]:_(s32) = G_TRUNC
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CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
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CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]]:_, [[AMT]]:_
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CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[AMT]]:_, [[C1]]:_
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CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[SRC]]:_, [[AND]]:_(s32)
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CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]]:_, [[C1]]:_
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CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[SRC]]:_, [[AND1]]:_(s32)
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CHECK: G_OR [[LSHR]]:_, [[SHL]]:_
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; Check G_ROTL
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CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
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CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]]:_, [[AMT]]:_
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CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[AMT]]:_, [[C1]]:_
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CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[SRC]]:_, [[AND]]:_(s32)
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CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]]:_, [[C1]]:_
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CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[SRC]]:_, [[AND1]]:_(s32)
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CHECK: G_OR [[SHL]]:_, [[LSHR]]:_
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)";
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// Check
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EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
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}
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// Test G_ROTL/G_ROTR non-pow2 lowering.
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TEST_F(AArch64GISelMITest, LowerRotatesNonPow2) {
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setUp();
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if (!TM)
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return;
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// Declare your legalization info
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DefineLegalizerInfo(A, {
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getActionDefinitionsBuilder({G_ROTR, G_ROTL}).lower(); });
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LLT S24 = LLT::scalar(24);
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auto Src = B.buildTrunc(S24, Copies[0]);
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auto Amt = B.buildTrunc(S24, Copies[1]);
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auto ROTR = B.buildInstr(TargetOpcode::G_ROTR, {S24}, {Src, Amt});
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auto ROTL = B.buildInstr(TargetOpcode::G_ROTL, {S24}, {Src, Amt});
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AInfo Info(MF->getSubtarget());
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DummyGISelObserver Observer;
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LegalizerHelper Helper(*MF, Info, Observer, B);
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// Perform Legalization
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EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,
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Helper.lower(*ROTR, 0, S24));
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EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,
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Helper.lower(*ROTL, 0, S24));
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auto CheckStr = R"(
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; Check G_ROTR
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CHECK: [[SRC:%[0-9]+]]:_(s24) = G_TRUNC
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CHECK: [[AMT:%[0-9]+]]:_(s24) = G_TRUNC
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CHECK: [[C:%[0-9]+]]:_(s24) = G_CONSTANT i24 0
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CHECK: [[C1:%[0-9]+]]:_(s24) = G_CONSTANT i24 23
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CHECK: [[C2:%[0-9]+]]:_(s24) = G_CONSTANT i24 24
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CHECK: [[UREM:%[0-9]+]]:_(s24) = G_UREM [[AMT]]:_, [[C2]]:_
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CHECK: [[LSHR:%[0-9]+]]:_(s24) = G_LSHR [[SRC]]:_, [[UREM]]:_(s24)
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CHECK: [[SUB:%[0-9]+]]:_(s24) = G_SUB [[C1]]:_, [[UREM]]:_
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CHECK: [[C4:%[0-9]+]]:_(s24) = G_CONSTANT i24 1
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CHECK: [[SHL:%[0-9]+]]:_(s24) = G_SHL [[SRC]]:_, [[C4]]:_(s24)
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CHECK: [[SHL2:%[0-9]+]]:_(s24) = G_SHL [[SHL]]:_, [[SUB]]:_(s24)
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CHECK: G_OR [[LSHR]]:_, [[SHL2]]:_
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; Check G_ROTL
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CHECK: [[C:%[0-9]+]]:_(s24) = G_CONSTANT i24 0
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CHECK: [[C1:%[0-9]+]]:_(s24) = G_CONSTANT i24 23
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CHECK: [[C2:%[0-9]+]]:_(s24) = G_CONSTANT i24 24
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CHECK: [[UREM:%[0-9]+]]:_(s24) = G_UREM [[AMT]]:_, [[C2]]:_
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CHECK: [[SHL:%[0-9]+]]:_(s24) = G_SHL [[SRC]]:_, [[UREM]]:_(s24)
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CHECK: [[SUB:%[0-9]+]]:_(s24) = G_SUB [[C1]]:_, [[UREM]]:_
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CHECK: [[C4:%[0-9]+]]:_(s24) = G_CONSTANT i24 1
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CHECK: [[LSHR:%[0-9]+]]:_(s24) = G_LSHR [[SRC]]:_, [[C4]]:_(s24)
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CHECK: [[LSHR2:%[0-9]+]]:_(s24) = G_LSHR [[LSHR]]:_, [[SUB]]:_(s24)
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CHECK: G_OR [[SHL]]:_, [[LSHR2]]:_
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)";
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// Check
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EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
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}
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// Test vector G_ROTR lowering.
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TEST_F(AArch64GISelMITest, LowerRotatesVector) {
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setUp();
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if (!TM)
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return;
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// Declare your legalization info
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DefineLegalizerInfo(A, {
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getActionDefinitionsBuilder({G_ROTR, G_ROTL}).lower(); });
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LLT S32 = LLT::scalar(32);
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LLT V4S32 = LLT::vector(4, S32);
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auto SrcTrunc = B.buildTrunc(S32, Copies[0]);
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auto Src = B.buildSplatVector(V4S32, SrcTrunc);
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auto AmtTrunc = B.buildTrunc(S32, Copies[1]);
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auto Amt = B.buildSplatVector(V4S32, AmtTrunc);
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auto ROTR = B.buildInstr(TargetOpcode::G_ROTR, {V4S32}, {Src, Amt});
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AInfo Info(MF->getSubtarget());
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DummyGISelObserver Observer;
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LegalizerHelper Helper(*MF, Info, Observer, B);
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// Perform Legalization
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EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,
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Helper.lower(*ROTR, 0, V4S32));
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auto CheckStr = R"(
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CHECK: [[SRCTRUNC:%[0-9]+]]:_(s32) = G_TRUNC
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CHECK: [[SRC:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[SRCTRUNC]]
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CHECK: [[AMTTRUNC:%[0-9]+]]:_(s32) = G_TRUNC
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CHECK: [[AMT:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AMTTRUNC]]
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CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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CHECK: [[ZERO:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]]
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CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
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CHECK: [[VEC31:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]]
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CHECK: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[ZERO]]:_, [[AMT]]:_
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CHECK: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[AMT]]:_, [[VEC31]]:_
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CHECK: [[LSHR:%[0-9]+]]:_(<4 x s32>) = G_LSHR [[SRC]]:_, [[AND]]:_(<4 x s32>)
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CHECK: [[AND1:%[0-9]+]]:_(<4 x s32>) = G_AND [[SUB]]:_, [[VEC31]]:_
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CHECK: [[SHL:%[0-9]+]]:_(<4 x s32>) = G_SHL [[SRC]]:_, [[AND1]]:_(<4 x s32>)
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CHECK: G_OR [[LSHR]]:_, [[SHL]]:_
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)";
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// Check
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EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
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}
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// Test CTTZ expansion when CTTZ_ZERO_UNDEF is legal or custom,
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// in which case it becomes CTTZ_ZERO_UNDEF with select.
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TEST_F(AArch64GISelMITest, LowerBitCountingCTTZ0) {
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