forked from OSchip/llvm-project
parent
d032c33300
commit
f5c90ec12c
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@ -5358,10 +5358,10 @@ SDOperand X86TargetLowering::LowerCAS(SDOperand Op, SelectionDAG &DAG) {
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case MVT::i32: Reg = X86::EAX; size = 4; break;
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case MVT::i32: Reg = X86::EAX; size = 4; break;
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};
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};
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SDOperand cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg,
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SDOperand cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg,
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Op.getOperand(2), SDOperand());
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Op.getOperand(3), SDOperand());
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SDOperand Ops[] = { cpIn.getValue(0),
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SDOperand Ops[] = { cpIn.getValue(0),
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Op.getOperand(1),
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Op.getOperand(1),
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Op.getOperand(3),
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Op.getOperand(2),
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DAG.getTargetConstant(size, MVT::i8),
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DAG.getTargetConstant(size, MVT::i8),
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cpIn.getValue(1) };
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cpIn.getValue(1) };
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SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
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SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
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@ -2548,6 +2548,7 @@ def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
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//FIXME: Please check the format Pseudo is certainly wrong, but the opcode and
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//FIXME: Please check the format Pseudo is certainly wrong, but the opcode and
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// prefixes should be correct
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// prefixes should be correct
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let Defs = [EAX, EFLAGS], Uses = [EAX] in {
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let Defs = [EAX, EFLAGS], Uses = [EAX] in {
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def CMPXCHG32 : I<0xB1, Pseudo, (outs), (ins i32mem:$ptr, GR32:$swap),
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def CMPXCHG32 : I<0xB1, Pseudo, (outs), (ins i32mem:$ptr, GR32:$swap),
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"cmpxchgl $swap,$ptr", []>, TB;
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"cmpxchgl $swap,$ptr", []>, TB;
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