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Add implicit def / use operands to MachineInstr. 

llvm-svn: 31632
This commit is contained in:
Evan Cheng 2006-11-10 08:32:14 +00:00
parent 13440b025c
commit f5bebe83a5
2 changed files with 20 additions and 6 deletions
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21
llvm/include/llvm/CodeGen/MachineInstr.h
View File

@ -60,6 +60,7 @@ private:
MachineOperandType opType:8; // Discriminate the union. MachineOperandType opType:8; // Discriminate the union.
bool IsDef : 1; // True if this is a def, false if this is a use. bool IsDef : 1; // True if this is a def, false if this is a use.
bool IsImp : 1; // True if this is an implicit def or use.
/// offset - Offset to address of global or external, only valid for /// offset - Offset to address of global or external, only valid for
/// MO_GlobalAddress, MO_ExternalSym and MO_ConstantPoolIndex /// MO_GlobalAddress, MO_ExternalSym and MO_ConstantPoolIndex
@ -78,6 +79,7 @@ public:
Op.opType = MachineOperand::MO_Immediate; Op.opType = MachineOperand::MO_Immediate;
Op.contents.immedVal = Val; Op.contents.immedVal = Val;
Op.IsDef = false; Op.IsDef = false;
Op.IsImp = false;
Op.offset = 0; Op.offset = 0;
return Op; return Op;
} }
@ -85,6 +87,7 @@ public:
const MachineOperand &operator=(const MachineOperand &MO) { const MachineOperand &operator=(const MachineOperand &MO) {
contents = MO.contents; contents = MO.contents;
IsDef = MO.IsDef; IsDef = MO.IsDef;
IsImp = MO.IsImp;
opType = MO.opType; opType = MO.opType;
offset = MO.offset; offset = MO.offset;
return *this; return *this;
@ -173,6 +176,15 @@ public:
IsDef = true; IsDef = true;
} }
bool isImplicit() const {
assert(isRegister() && "Wrong MachineOperand accessor");
return IsImp;
}
bool setImplicit() {
assert(isRegister() && "Wrong MachineOperand accessor");
IsImp = true;
}
/// getReg - Returns the register number. /// getReg - Returns the register number.
/// ///
unsigned getReg() const { unsigned getReg() const {
@ -330,10 +342,11 @@ public:
/// addRegOperand - Add a register operand. /// addRegOperand - Add a register operand.
/// ///
void addRegOperand(unsigned Reg, bool IsDef) { void addRegOperand(unsigned Reg, bool IsDef, bool IsImp = false) {
MachineOperand &Op = AddNewOperand(); MachineOperand &Op = AddNewOperand(IsImp);
Op.opType = MachineOperand::MO_Register; Op.opType = MachineOperand::MO_Register;
Op.IsDef = IsDef; Op.IsDef = IsDef;
Op.IsImp = IsImp;
Op.contents.RegNo = Reg; Op.contents.RegNo = Reg;
Op.offset = 0; Op.offset = 0;
} }
@ -415,8 +428,8 @@ public:
Operands.erase(Operands.begin()+i); Operands.erase(Operands.begin()+i);
} }
private: private:
MachineOperand &AddNewOperand() { MachineOperand &AddNewOperand(bool IsImp = false) {
assert(!OperandsComplete() && assert((IsImp || !OperandsComplete()) &&
"Trying to add an operand to a machine instr that is already done!"); "Trying to add an operand to a machine instr that is already done!");
Operands.push_back(MachineOperand()); Operands.push_back(MachineOperand());
return Operands.back(); return Operands.back();

5
llvm/include/llvm/CodeGen/MachineInstrBuilder.h
View File

@ -33,8 +33,9 @@ public:
/// addReg - Add a new virtual register operand... /// addReg - Add a new virtual register operand...
/// ///
const MachineInstrBuilder &addReg(int RegNo, bool isDef = false) const { const MachineInstrBuilder &addReg(int RegNo, bool isDef = false,
MI->addRegOperand(RegNo, isDef); bool isImp = false) const {
MI->addRegOperand(RegNo, isDef, isImp);
return *this; return *this;
} }