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[XCore] Add TSETR instruction. 

This instruction is not targeted by the compiler but it is needed for the
MC layer.

llvm-svn: 175406
This commit is contained in:
Richard Osborne 2013-02-17 22:32:41 +00:00
parent e3e3feea3c
commit f5a3ffcba9
4 changed files with 37 additions and 1 deletions
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21
llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
View File

@ -140,6 +140,11 @@ static DecodeStatus Decode3RInstruction(MCInst &Inst,
uint64_t Address,
const void *Decoder);
static DecodeStatus Decode3RImmInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus Decode2RUSInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
@ -313,6 +318,9 @@ Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
case 0x16:
Inst.setOpcode(XCore::EQ_2rus);
return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
case 0x17:
Inst.setOpcode(XCore::TSETR_3r);
return Decode3RImmInstruction(Inst, Insn, Address, Decoder);
case 0x18:
Inst.setOpcode(XCore::LSS_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
@ -515,6 +523,19 @@ Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
return S;
}
static DecodeStatus
Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2, Op3;
DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
if (S == MCDisassembler::Success) {
Inst.addOperand(MCOperand::CreateImm(Op1));
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
}
return S;
}
static DecodeStatus
Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {

8
llvm/lib/Target/XCore/XCoreInstrFormats.td
View File

@ -39,6 +39,14 @@ class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
let DecoderMethod = "Decode3RInstruction";
}
// 3R with first operand as an immediate. Used for TSETR where the first
// operand is treated as an immediate since it refers to a register number in
// another thread.
class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
: _F3R<opc, outs, ins, asmstr, pattern> {
let DecoderMethod = "Decode3RImmInstruction";
}
class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> {
let Inst{31-27} = opc{8-4};

6
llvm/lib/Target/XCore/XCoreInstrInfo.td
View File

@ -395,7 +395,11 @@ def STW_2rus : _F2RUS<0b0000, (outs),
defm SHL : F3R_2RBITP<0b00100, 0b10100, "shl", shl>;
defm SHR : F3R_2RBITP<0b00101, 0b10101, "shr", srl>;
// TODO tsetr
// The first operand is treated as an immediate since it refers to a register
// number in another thread.
def TSETR_3r : _F3RImm<0b10111, (outs), (ins i32imm:$a, GRRegs:$b, GRRegs:$c),
"set t[$c]:r$a, $b", []>;
// Three operand long
def LDAWF_l3r : _FL3R<0b000111100, (outs GRRegs:$dst),

3
llvm/test/MC/Disassembler/XCore/xcore.txt
View File

@ -325,6 +325,9 @@
# CHECK: sub r4, r2, r5
0x89 0x1a
# CHECK: set t[r0]:r1, r2
0x18 0xb8
# 2rus instructions
# CHECK: add r10, r2, 5