From f5917e0312edacf1fe4cfebc532e3a78c854adee Mon Sep 17 00:00:00 2001
From: Carl Ritson <carl.ritson@amd.com>
Date: Fri, 16 Jul 2021 12:13:29 +0900
Subject: [PATCH] [TableGen] Allow isAllocatable inheritence from any
 superclass

When setting Allocatable on a generated register class check all
superclasses and set Allocatable true if any superclass is
allocatable.

Without this change generated register classes based on an
allocatable class may end up unallocatable due to the topological
inheritance order.

This change primarily effects AMDGPU backend; however, there are
a few changes in MIPs GlobalISel register constraints as a result.

Reviewed By: kparzysz

Differential Revision: https://reviews.llvm.org/D105967
---
 llvm/utils/TableGen/CodeGenRegisters.cpp | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/llvm/utils/TableGen/CodeGenRegisters.cpp b/llvm/utils/TableGen/CodeGenRegisters.cpp
index db15bac9c3f8..930b7742103e 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/CodeGenRegisters.cpp
@@ -833,7 +833,10 @@ void CodeGenRegisterClass::inheritProperties(CodeGenRegBank &RegBank) {
   Namespace = Super.Namespace;
   VTs = Super.VTs;
   CopyCost = Super.CopyCost;
-  Allocatable = Super.Allocatable;
+  // Check for allocatable superclasses.
+  Allocatable = any_of(SuperClasses, [&](const CodeGenRegisterClass *S) {
+    return S->Allocatable;
+  });
   AltOrderSelect = Super.AltOrderSelect;
   AllocationPriority = Super.AllocationPriority;
   GeneratePressureSet |= Super.GeneratePressureSet;