forked from OSchip/llvm-project
[InstCombine] use m_APInt to allow icmp X, C folds for splat constant vectors
isSignBitCheck could be changed to take a pointer param to avoid the 'UnusedBit' ugliness. llvm-svn: 281231
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@ -3153,9 +3153,10 @@ Instruction *InstCombiner::foldICmpUsingKnownBits(ICmpInst &I) {
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// If this is a normal comparison, it demands all bits. If it is a sign bit
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// comparison, it only demands the sign bit.
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bool IsSignBit = false;
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if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
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const APInt *CmpC;
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if (match(Op1, m_APInt(CmpC))) {
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bool UnusedBit;
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IsSignBit = isSignBitCheck(Pred, CI->getValue(), UnusedBit);
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IsSignBit = isSignBitCheck(Pred, *CmpC, UnusedBit);
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}
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APInt Op0KnownZero(BitWidth, 0), Op0KnownOne(BitWidth, 0);
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@ -628,11 +628,9 @@ define i1 @test35(i32 %X) {
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ret i1 %tmp2
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}
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; FIXME: Vectors should fold the same way.
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define <2 x i1> @test35vec(<2 x i32> %X) {
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; CHECK-LABEL: @test35vec(
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; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i32> %X, <i32 7, i32 7>
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; CHECK-NEXT: [[TMP2:%.*]] = icmp slt <2 x i32> [[TMP1]], zeroinitializer
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; CHECK-NEXT: [[TMP2:%.*]] = icmp slt <2 x i32> %X, zeroinitializer
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; CHECK-NEXT: ret <2 x i1> [[TMP2]]
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;
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%tmp1 = ashr <2 x i32> %X, <i32 7, i32 7>
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@ -3,8 +3,8 @@
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define <4 x i32> @psignd_3(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: @psignd_3(
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; CHECK-NEXT: [[B_LOBIT:%.*]] = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, %a
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; CHECK-NEXT: [[B_LOBIT:%.*]] = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
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; CHECK-NEXT: [[T1:%.*]] = xor <4 x i32> [[B_LOBIT]], <i32 -1, i32 -1, i32 -1, i32 -1>
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; CHECK-NEXT: [[T2:%.*]] = and <4 x i32> %a, [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = and <4 x i32> [[B_LOBIT]], [[SUB]]
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@ -25,8 +25,8 @@ define <4 x i32> @psignd_3(<4 x i32> %a, <4 x i32> %b) {
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define <4 x i32> @test1(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: [[B_LOBIT:%.*]] = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, %a
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; CHECK-NEXT: [[B_LOBIT:%.*]] = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
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; CHECK-NEXT: [[B_LOBIT_NOT:%.*]] = xor <4 x i32> [[B_LOBIT]], <i32 -1, i32 -1, i32 -1, i32 -1>
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; CHECK-NEXT: [[T2:%.*]] = and <4 x i32> [[B_LOBIT]], %a
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; CHECK-NEXT: [[T3:%.*]] = and <4 x i32> [[B_LOBIT_NOT]], [[SUB]]
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