forked from OSchip/llvm-project
Add register encoding support in X86 backend
- Add 'HwEncoding' for X86 registers and call getEncodingValue() to retrieve their encoding values. - This's the first step to adopt new scheme. Furthur revising is onging. llvm-svn: 165241
This commit is contained in:
Michael Liao
parent
058666a8d0
commit
f54249b55f
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@ -16,6 +16,7 @@
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#include "MCTargetDesc/X86BaseInfo.h"
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#include "MCTargetDesc/X86FixupKinds.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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@ -51,8 +52,8 @@ public:
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return (STI.getFeatureBits() & X86::Mode64Bit) == 0;
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}
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static unsigned GetX86RegNum(const MCOperand &MO) {
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return X86_MC::getX86RegNum(MO.getReg());
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unsigned GetX86RegNum(const MCOperand &MO) const {
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return Ctx.getRegisterInfo().getEncodingValue(MO.getReg()) & 0x7;
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}
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// On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
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@ -64,8 +65,8 @@ public:
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// VEX.VVVV => XMM9 => ~9
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//
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// See table 4-35 of Intel AVX Programming Reference for details.
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static unsigned char getVEXRegisterEncoding(const MCInst &MI,
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unsigned OpNum) {
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unsigned char getVEXRegisterEncoding(const MCInst &MI,
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unsigned OpNum) const {
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unsigned SrcReg = MI.getOperand(OpNum).getReg();
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unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
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if (X86II::isX86_64ExtendedReg(SrcReg))
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@ -209,122 +209,10 @@ unsigned X86_MC::getDwarfRegFlavour(StringRef TT, bool isEH) {
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return DWARFFlavour::X86_32_Generic;
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}
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/// getX86RegNum - This function maps LLVM register identifiers to their X86
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/// specific numbering, which is used in various places encoding instructions.
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unsigned X86_MC::getX86RegNum(unsigned RegNo) {
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switch(RegNo) {
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case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
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case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
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case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
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case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
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case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
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return N86::ESP;
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case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
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return N86::EBP;
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case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
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return N86::ESI;
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case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
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return N86::EDI;
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case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
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return N86::EAX;
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case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
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return N86::ECX;
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case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
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return N86::EDX;
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case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
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return N86::EBX;
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case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
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return N86::ESP;
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case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
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return N86::EBP;
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case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
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return N86::ESI;
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case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
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return N86::EDI;
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case X86::ST0: return 0;
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case X86::ST1: return 1;
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case X86::ST2: return 2;
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case X86::ST3: return 3;
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case X86::ST4: return 4;
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case X86::ST5: return 5;
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case X86::ST6: return 6;
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case X86::ST7: return 7;
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case X86::XMM0: case X86::XMM8:
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case X86::YMM0: case X86::YMM8: case X86::MM0:
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return 0;
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case X86::XMM1: case X86::XMM9:
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case X86::YMM1: case X86::YMM9: case X86::MM1:
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return 1;
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case X86::XMM2: case X86::XMM10:
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case X86::YMM2: case X86::YMM10: case X86::MM2:
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return 2;
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case X86::XMM3: case X86::XMM11:
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case X86::YMM3: case X86::YMM11: case X86::MM3:
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return 3;
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case X86::XMM4: case X86::XMM12:
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case X86::YMM4: case X86::YMM12: case X86::MM4:
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return 4;
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case X86::XMM5: case X86::XMM13:
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case X86::YMM5: case X86::YMM13: case X86::MM5:
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return 5;
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case X86::XMM6: case X86::XMM14:
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case X86::YMM6: case X86::YMM14: case X86::MM6:
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return 6;
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case X86::XMM7: case X86::XMM15:
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case X86::YMM7: case X86::YMM15: case X86::MM7:
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return 7;
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case X86::ES: return 0;
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case X86::CS: return 1;
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case X86::SS: return 2;
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case X86::DS: return 3;
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case X86::FS: return 4;
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case X86::GS: return 5;
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case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
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case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
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case X86::CR2: case X86::CR10: case X86::DR2: return 2;
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case X86::CR3: case X86::CR11: case X86::DR3: return 3;
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case X86::CR4: case X86::CR12: case X86::DR4: return 4;
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case X86::CR5: case X86::CR13: case X86::DR5: return 5;
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case X86::CR6: case X86::CR14: case X86::DR6: return 6;
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case X86::CR7: case X86::CR15: case X86::DR7: return 7;
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// Pseudo index registers are equivalent to a "none"
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// scaled index (See Intel Manual 2A, table 2-3)
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case X86::EIZ:
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case X86::RIZ:
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return 4;
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default:
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assert((int(RegNo) > 0) && "Unknown physical register!");
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return 0;
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}
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}
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void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
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// FIXME: TableGen these.
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for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
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int SEH = X86_MC::getX86RegNum(Reg);
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switch (Reg) {
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case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
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case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
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case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
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case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
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case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
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case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
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case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
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case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
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case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
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case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
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case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
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case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
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SEH += 8;
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break;
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}
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unsigned SEH = MRI->getEncodingValue(Reg);
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MRI->mapLLVMRegToSEHReg(Reg, SEH);
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}
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}
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@ -64,8 +64,6 @@ namespace X86_MC {
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unsigned getDwarfRegFlavour(StringRef TT, bool isEH);
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unsigned getX86RegNum(unsigned RegNo);
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void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI);
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/// createX86MCSubtargetInfo - Create a X86 MCSubtargetInfo instance.
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@ -109,6 +109,14 @@ namespace {
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void emitMemModRMByte(const MachineInstr &MI,
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unsigned Op, unsigned RegOpcodeField,
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intptr_t PCAdj = 0);
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unsigned getX86RegNum(unsigned RegNo) const {
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const TargetRegisterInfo *TRI = TM.getRegisterInfo();
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return TRI->getEncodingValue(RegNo) & 0x7;
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}
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unsigned char getVEXRegisterEncoding(const MachineInstr &MI,
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unsigned OpNum) const;
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};
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template<class CodeEmitter>
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@ -363,7 +371,7 @@ inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
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template<class CodeEmitter>
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void Emitter<CodeEmitter>::emitRegModRMByte(unsigned ModRMReg,
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unsigned RegOpcodeFld){
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MCE.emitByte(ModRMByte(3, RegOpcodeFld, X86_MC::getX86RegNum(ModRMReg)));
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MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
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}
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template<class CodeEmitter>
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@ -501,7 +509,7 @@ void Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI,
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// 2-7) and absolute references.
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unsigned BaseRegNo = -1U;
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if (BaseReg != 0 && BaseReg != X86::RIP)
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BaseRegNo = X86_MC::getX86RegNum(BaseReg);
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BaseRegNo = getX86RegNum(BaseReg);
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if (// The SIB byte must be used if there is an index register.
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IndexReg.getReg() == 0 &&
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@ -577,15 +585,15 @@ void Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI,
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// Manual 2A, table 2-7. The displacement has already been output.
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unsigned IndexRegNo;
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if (IndexReg.getReg())
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IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg());
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IndexRegNo = getX86RegNum(IndexReg.getReg());
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else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
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IndexRegNo = 4;
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emitSIBByte(SS, IndexRegNo, 5);
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} else {
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unsigned BaseRegNo = X86_MC::getX86RegNum(BaseReg);
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unsigned BaseRegNo = getX86RegNum(BaseReg);
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unsigned IndexRegNo;
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if (IndexReg.getReg())
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IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg());
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IndexRegNo = getX86RegNum(IndexReg.getReg());
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else
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IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
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emitSIBByte(SS, IndexRegNo, BaseRegNo);
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@ -756,10 +764,12 @@ void Emitter<CodeEmitter>::emitOpcodePrefix(uint64_t TSFlags,
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// VEX.VVVV => XMM9 => ~9
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//
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// See table 4-35 of Intel AVX Programming Reference for details.
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static unsigned char getVEXRegisterEncoding(const MachineInstr &MI,
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unsigned OpNum) {
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template<class CodeEmitter>
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unsigned char
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Emitter<CodeEmitter>::getVEXRegisterEncoding(const MachineInstr &MI,
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unsigned OpNum) const {
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unsigned SrcReg = MI.getOperand(OpNum).getReg();
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unsigned SrcRegNum = X86_MC::getX86RegNum(MI.getOperand(OpNum).getReg());
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unsigned SrcRegNum = getX86RegNum(MI.getOperand(OpNum).getReg());
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if (X86II::isX86_64ExtendedReg(SrcReg))
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SrcRegNum |= 8;
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@ -1235,7 +1245,7 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
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case X86II::AddRegFrm: {
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MCE.emitByte(BaseOpcode +
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X86_MC::getX86RegNum(MI.getOperand(CurOp++).getReg()));
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getX86RegNum(MI.getOperand(CurOp++).getReg()));
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if (CurOp == NumOps)
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break;
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@ -1270,7 +1280,7 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
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case X86II::MRMDestReg: {
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MCE.emitByte(BaseOpcode);
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emitRegModRMByte(MI.getOperand(CurOp).getReg(),
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X86_MC::getX86RegNum(MI.getOperand(CurOp+1).getReg()));
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getX86RegNum(MI.getOperand(CurOp+1).getReg()));
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CurOp += 2;
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break;
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}
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@ -1281,7 +1291,7 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
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if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
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SrcRegNum++;
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emitMemModRMByte(MI, CurOp,
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X86_MC::getX86RegNum(MI.getOperand(SrcRegNum).getReg()));
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getX86RegNum(MI.getOperand(SrcRegNum).getReg()));
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CurOp = SrcRegNum + 1;
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break;
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}
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@ -1297,7 +1307,7 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
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++SrcRegNum;
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emitRegModRMByte(MI.getOperand(SrcRegNum).getReg(),
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X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg()));
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getX86RegNum(MI.getOperand(CurOp).getReg()));
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// 2 operands skipped with HasMemOp4, compensate accordingly
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CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1;
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if (HasVEX_4VOp3)
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@ -1319,7 +1329,7 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
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intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ?
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X86II::getSizeOfImm(Desc->TSFlags) : 0;
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emitMemModRMByte(MI, FirstMemOp,
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X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg()),PCAdj);
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getX86RegNum(MI.getOperand(CurOp).getReg()),PCAdj);
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CurOp += AddrOperands + 1;
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if (HasVEX_4VOp3)
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++CurOp;
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@ -1409,7 +1419,7 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
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MCE.emitByte(BaseOpcode);
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// Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
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emitRegModRMByte(MI.getOperand(CurOp).getReg(),
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X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg()));
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getX86RegNum(MI.getOperand(CurOp).getReg()));
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++CurOp;
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break;
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@ -1442,7 +1452,7 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
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const MachineOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand
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: CurOp);
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++CurOp;
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unsigned RegNum = X86_MC::getX86RegNum(MO.getReg()) << 4;
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unsigned RegNum = getX86RegNum(MO.getReg()) << 4;
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if (X86II::isX86_64ExtendedReg(MO.getReg()))
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RegNum |= 1 << 7;
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// If there is an additional 5th operand it must be an immediate, which
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@ -10412,6 +10412,7 @@ SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
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DebugLoc dl = Op.getDebugLoc();
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const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
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const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
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if (Subtarget->is64Bit()) {
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SDValue OutChains[6];
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@ -10420,8 +10421,8 @@ SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
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const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
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const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
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const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
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const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
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const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
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const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
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const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
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@ -10523,7 +10524,7 @@ SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
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// This is storing the opcode for MOV32ri.
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const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
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const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
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const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
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OutChains[0] = DAG.getStore(Root, dl,
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DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
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Trmp, MachinePointerInfo(TrmpAddr),
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@ -106,23 +106,7 @@ X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
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int
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X86RegisterInfo::getSEHRegNum(unsigned i) const {
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int reg = X86_MC::getX86RegNum(i);
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switch (i) {
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case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
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case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
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case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
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case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
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case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
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case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
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case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
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case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
|
||||
case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
|
||||
case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
|
||||
case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
|
||||
case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
|
||||
reg += 8;
|
||||
}
|
||||
return reg;
|
||||
return getEncodingValue(i);
|
||||
}
|
||||
|
||||
const TargetRegisterClass *
|
||||
|
|
|
|||
|
|
@ -58,10 +58,6 @@ private:
|
|||
public:
|
||||
X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii);
|
||||
|
||||
/// getX86RegNum - Returns the native X86 register number for the given LLVM
|
||||
/// register identifier.
|
||||
static unsigned getX86RegNum(unsigned RegNo);
|
||||
|
||||
// FIXME: This should be tablegen'd like getDwarfRegNum is
|
||||
int getSEHRegNum(unsigned i) const;
|
||||
|
||||
|
|
|
|||
|
|
@ -13,258 +13,264 @@
|
|||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Register definitions...
|
||||
//
|
||||
let Namespace = "X86" in {
|
||||
class X86Reg<string n, bits<16> Enc, list<Register> subregs = []> : Register<n> {
|
||||
let Namespace = "X86";
|
||||
let HWEncoding = Enc;
|
||||
let SubRegs = subregs;
|
||||
}
|
||||
|
||||
// Subregister indices.
|
||||
// Subregister indices.
|
||||
let Namespace = "X86" in {
|
||||
def sub_8bit : SubRegIndex;
|
||||
def sub_8bit_hi : SubRegIndex;
|
||||
def sub_16bit : SubRegIndex;
|
||||
def sub_32bit : SubRegIndex;
|
||||
def sub_xmm : SubRegIndex;
|
||||
|
||||
|
||||
// In the register alias definitions below, we define which registers alias
|
||||
// which others. We only specify which registers the small registers alias,
|
||||
// because the register file generator is smart enough to figure out that
|
||||
// AL aliases AX if we tell it that AX aliased AL (for example).
|
||||
|
||||
// Dwarf numbering is different for 32-bit and 64-bit, and there are
|
||||
// variations by target as well. Currently the first entry is for X86-64,
|
||||
// second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux
|
||||
// and debug information on X86-32/Darwin)
|
||||
|
||||
// 8-bit registers
|
||||
// Low registers
|
||||
def AL : Register<"al">;
|
||||
def DL : Register<"dl">;
|
||||
def CL : Register<"cl">;
|
||||
def BL : Register<"bl">;
|
||||
|
||||
// X86-64 only, requires REX.
|
||||
let CostPerUse = 1 in {
|
||||
def SIL : Register<"sil">;
|
||||
def DIL : Register<"dil">;
|
||||
def BPL : Register<"bpl">;
|
||||
def SPL : Register<"spl">;
|
||||
def R8B : Register<"r8b">;
|
||||
def R9B : Register<"r9b">;
|
||||
def R10B : Register<"r10b">;
|
||||
def R11B : Register<"r11b">;
|
||||
def R12B : Register<"r12b">;
|
||||
def R13B : Register<"r13b">;
|
||||
def R14B : Register<"r14b">;
|
||||
def R15B : Register<"r15b">;
|
||||
}
|
||||
|
||||
// High registers. On x86-64, these cannot be used in any instruction
|
||||
// with a REX prefix.
|
||||
def AH : Register<"ah">;
|
||||
def DH : Register<"dh">;
|
||||
def CH : Register<"ch">;
|
||||
def BH : Register<"bh">;
|
||||
|
||||
// 16-bit registers
|
||||
let SubRegIndices = [sub_8bit, sub_8bit_hi], CoveredBySubRegs = 1 in {
|
||||
def AX : RegisterWithSubRegs<"ax", [AL,AH]>;
|
||||
def DX : RegisterWithSubRegs<"dx", [DL,DH]>;
|
||||
def CX : RegisterWithSubRegs<"cx", [CL,CH]>;
|
||||
def BX : RegisterWithSubRegs<"bx", [BL,BH]>;
|
||||
}
|
||||
let SubRegIndices = [sub_8bit] in {
|
||||
def SI : RegisterWithSubRegs<"si", [SIL]>;
|
||||
def DI : RegisterWithSubRegs<"di", [DIL]>;
|
||||
def BP : RegisterWithSubRegs<"bp", [BPL]>;
|
||||
def SP : RegisterWithSubRegs<"sp", [SPL]>;
|
||||
}
|
||||
def IP : Register<"ip">;
|
||||
|
||||
// X86-64 only, requires REX.
|
||||
let SubRegIndices = [sub_8bit], CostPerUse = 1 in {
|
||||
def R8W : RegisterWithSubRegs<"r8w", [R8B]>;
|
||||
def R9W : RegisterWithSubRegs<"r9w", [R9B]>;
|
||||
def R10W : RegisterWithSubRegs<"r10w", [R10B]>;
|
||||
def R11W : RegisterWithSubRegs<"r11w", [R11B]>;
|
||||
def R12W : RegisterWithSubRegs<"r12w", [R12B]>;
|
||||
def R13W : RegisterWithSubRegs<"r13w", [R13B]>;
|
||||
def R14W : RegisterWithSubRegs<"r14w", [R14B]>;
|
||||
def R15W : RegisterWithSubRegs<"r15w", [R15B]>;
|
||||
}
|
||||
// 32-bit registers
|
||||
let SubRegIndices = [sub_16bit] in {
|
||||
def EAX : RegisterWithSubRegs<"eax", [AX]>, DwarfRegNum<[-2, 0, 0]>;
|
||||
def EDX : RegisterWithSubRegs<"edx", [DX]>, DwarfRegNum<[-2, 2, 2]>;
|
||||
def ECX : RegisterWithSubRegs<"ecx", [CX]>, DwarfRegNum<[-2, 1, 1]>;
|
||||
def EBX : RegisterWithSubRegs<"ebx", [BX]>, DwarfRegNum<[-2, 3, 3]>;
|
||||
def ESI : RegisterWithSubRegs<"esi", [SI]>, DwarfRegNum<[-2, 6, 6]>;
|
||||
def EDI : RegisterWithSubRegs<"edi", [DI]>, DwarfRegNum<[-2, 7, 7]>;
|
||||
def EBP : RegisterWithSubRegs<"ebp", [BP]>, DwarfRegNum<[-2, 4, 5]>;
|
||||
def ESP : RegisterWithSubRegs<"esp", [SP]>, DwarfRegNum<[-2, 5, 4]>;
|
||||
def EIP : RegisterWithSubRegs<"eip", [IP]>, DwarfRegNum<[-2, 8, 8]>;
|
||||
|
||||
// X86-64 only, requires REX
|
||||
let CostPerUse = 1 in {
|
||||
def R8D : RegisterWithSubRegs<"r8d", [R8W]>;
|
||||
def R9D : RegisterWithSubRegs<"r9d", [R9W]>;
|
||||
def R10D : RegisterWithSubRegs<"r10d", [R10W]>;
|
||||
def R11D : RegisterWithSubRegs<"r11d", [R11W]>;
|
||||
def R12D : RegisterWithSubRegs<"r12d", [R12W]>;
|
||||
def R13D : RegisterWithSubRegs<"r13d", [R13W]>;
|
||||
def R14D : RegisterWithSubRegs<"r14d", [R14W]>;
|
||||
def R15D : RegisterWithSubRegs<"r15d", [R15W]>;
|
||||
}}
|
||||
|
||||
// 64-bit registers, X86-64 only
|
||||
let SubRegIndices = [sub_32bit] in {
|
||||
def RAX : RegisterWithSubRegs<"rax", [EAX]>, DwarfRegNum<[0, -2, -2]>;
|
||||
def RDX : RegisterWithSubRegs<"rdx", [EDX]>, DwarfRegNum<[1, -2, -2]>;
|
||||
def RCX : RegisterWithSubRegs<"rcx", [ECX]>, DwarfRegNum<[2, -2, -2]>;
|
||||
def RBX : RegisterWithSubRegs<"rbx", [EBX]>, DwarfRegNum<[3, -2, -2]>;
|
||||
def RSI : RegisterWithSubRegs<"rsi", [ESI]>, DwarfRegNum<[4, -2, -2]>;
|
||||
def RDI : RegisterWithSubRegs<"rdi", [EDI]>, DwarfRegNum<[5, -2, -2]>;
|
||||
def RBP : RegisterWithSubRegs<"rbp", [EBP]>, DwarfRegNum<[6, -2, -2]>;
|
||||
def RSP : RegisterWithSubRegs<"rsp", [ESP]>, DwarfRegNum<[7, -2, -2]>;
|
||||
|
||||
// These also require REX.
|
||||
let CostPerUse = 1 in {
|
||||
def R8 : RegisterWithSubRegs<"r8", [R8D]>, DwarfRegNum<[8, -2, -2]>;
|
||||
def R9 : RegisterWithSubRegs<"r9", [R9D]>, DwarfRegNum<[9, -2, -2]>;
|
||||
def R10 : RegisterWithSubRegs<"r10", [R10D]>, DwarfRegNum<[10, -2, -2]>;
|
||||
def R11 : RegisterWithSubRegs<"r11", [R11D]>, DwarfRegNum<[11, -2, -2]>;
|
||||
def R12 : RegisterWithSubRegs<"r12", [R12D]>, DwarfRegNum<[12, -2, -2]>;
|
||||
def R13 : RegisterWithSubRegs<"r13", [R13D]>, DwarfRegNum<[13, -2, -2]>;
|
||||
def R14 : RegisterWithSubRegs<"r14", [R14D]>, DwarfRegNum<[14, -2, -2]>;
|
||||
def R15 : RegisterWithSubRegs<"r15", [R15D]>, DwarfRegNum<[15, -2, -2]>;
|
||||
def RIP : RegisterWithSubRegs<"rip", [EIP]>, DwarfRegNum<[16, -2, -2]>;
|
||||
}}
|
||||
|
||||
// MMX Registers. These are actually aliased to ST0 .. ST7
|
||||
def MM0 : Register<"mm0">, DwarfRegNum<[41, 29, 29]>;
|
||||
def MM1 : Register<"mm1">, DwarfRegNum<[42, 30, 30]>;
|
||||
def MM2 : Register<"mm2">, DwarfRegNum<[43, 31, 31]>;
|
||||
def MM3 : Register<"mm3">, DwarfRegNum<[44, 32, 32]>;
|
||||
def MM4 : Register<"mm4">, DwarfRegNum<[45, 33, 33]>;
|
||||
def MM5 : Register<"mm5">, DwarfRegNum<[46, 34, 34]>;
|
||||
def MM6 : Register<"mm6">, DwarfRegNum<[47, 35, 35]>;
|
||||
def MM7 : Register<"mm7">, DwarfRegNum<[48, 36, 36]>;
|
||||
|
||||
// Pseudo Floating Point registers
|
||||
def FP0 : Register<"fp0">;
|
||||
def FP1 : Register<"fp1">;
|
||||
def FP2 : Register<"fp2">;
|
||||
def FP3 : Register<"fp3">;
|
||||
def FP4 : Register<"fp4">;
|
||||
def FP5 : Register<"fp5">;
|
||||
def FP6 : Register<"fp6">;
|
||||
|
||||
// XMM Registers, used by the various SSE instruction set extensions.
|
||||
def XMM0: Register<"xmm0">, DwarfRegNum<[17, 21, 21]>;
|
||||
def XMM1: Register<"xmm1">, DwarfRegNum<[18, 22, 22]>;
|
||||
def XMM2: Register<"xmm2">, DwarfRegNum<[19, 23, 23]>;
|
||||
def XMM3: Register<"xmm3">, DwarfRegNum<[20, 24, 24]>;
|
||||
def XMM4: Register<"xmm4">, DwarfRegNum<[21, 25, 25]>;
|
||||
def XMM5: Register<"xmm5">, DwarfRegNum<[22, 26, 26]>;
|
||||
def XMM6: Register<"xmm6">, DwarfRegNum<[23, 27, 27]>;
|
||||
def XMM7: Register<"xmm7">, DwarfRegNum<[24, 28, 28]>;
|
||||
|
||||
// X86-64 only
|
||||
let CostPerUse = 1 in {
|
||||
def XMM8: Register<"xmm8">, DwarfRegNum<[25, -2, -2]>;
|
||||
def XMM9: Register<"xmm9">, DwarfRegNum<[26, -2, -2]>;
|
||||
def XMM10: Register<"xmm10">, DwarfRegNum<[27, -2, -2]>;
|
||||
def XMM11: Register<"xmm11">, DwarfRegNum<[28, -2, -2]>;
|
||||
def XMM12: Register<"xmm12">, DwarfRegNum<[29, -2, -2]>;
|
||||
def XMM13: Register<"xmm13">, DwarfRegNum<[30, -2, -2]>;
|
||||
def XMM14: Register<"xmm14">, DwarfRegNum<[31, -2, -2]>;
|
||||
def XMM15: Register<"xmm15">, DwarfRegNum<[32, -2, -2]>;
|
||||
} // CostPerUse
|
||||
|
||||
// YMM Registers, used by AVX instructions
|
||||
let SubRegIndices = [sub_xmm] in {
|
||||
def YMM0: RegisterWithSubRegs<"ymm0", [XMM0]>, DwarfRegAlias<XMM0>;
|
||||
def YMM1: RegisterWithSubRegs<"ymm1", [XMM1]>, DwarfRegAlias<XMM1>;
|
||||
def YMM2: RegisterWithSubRegs<"ymm2", [XMM2]>, DwarfRegAlias<XMM2>;
|
||||
def YMM3: RegisterWithSubRegs<"ymm3", [XMM3]>, DwarfRegAlias<XMM3>;
|
||||
def YMM4: RegisterWithSubRegs<"ymm4", [XMM4]>, DwarfRegAlias<XMM4>;
|
||||
def YMM5: RegisterWithSubRegs<"ymm5", [XMM5]>, DwarfRegAlias<XMM5>;
|
||||
def YMM6: RegisterWithSubRegs<"ymm6", [XMM6]>, DwarfRegAlias<XMM6>;
|
||||
def YMM7: RegisterWithSubRegs<"ymm7", [XMM7]>, DwarfRegAlias<XMM7>;
|
||||
def YMM8: RegisterWithSubRegs<"ymm8", [XMM8]>, DwarfRegAlias<XMM8>;
|
||||
def YMM9: RegisterWithSubRegs<"ymm9", [XMM9]>, DwarfRegAlias<XMM9>;
|
||||
def YMM10: RegisterWithSubRegs<"ymm10", [XMM10]>, DwarfRegAlias<XMM10>;
|
||||
def YMM11: RegisterWithSubRegs<"ymm11", [XMM11]>, DwarfRegAlias<XMM11>;
|
||||
def YMM12: RegisterWithSubRegs<"ymm12", [XMM12]>, DwarfRegAlias<XMM12>;
|
||||
def YMM13: RegisterWithSubRegs<"ymm13", [XMM13]>, DwarfRegAlias<XMM13>;
|
||||
def YMM14: RegisterWithSubRegs<"ymm14", [XMM14]>, DwarfRegAlias<XMM14>;
|
||||
def YMM15: RegisterWithSubRegs<"ymm15", [XMM15]>, DwarfRegAlias<XMM15>;
|
||||
}
|
||||
|
||||
class STRegister<string Name, list<Register> A> : Register<Name> {
|
||||
let Aliases = A;
|
||||
}
|
||||
|
||||
// Floating point stack registers. These don't map one-to-one to the FP
|
||||
// pseudo registers, but we still mark them as aliasing FP registers. That
|
||||
// way both kinds can be live without exceeding the stack depth. ST registers
|
||||
// are only live around inline assembly.
|
||||
def ST0 : STRegister<"st(0)", []>, DwarfRegNum<[33, 12, 11]>;
|
||||
def ST1 : STRegister<"st(1)", [FP6]>, DwarfRegNum<[34, 13, 12]>;
|
||||
def ST2 : STRegister<"st(2)", [FP5]>, DwarfRegNum<[35, 14, 13]>;
|
||||
def ST3 : STRegister<"st(3)", [FP4]>, DwarfRegNum<[36, 15, 14]>;
|
||||
def ST4 : STRegister<"st(4)", [FP3]>, DwarfRegNum<[37, 16, 15]>;
|
||||
def ST5 : STRegister<"st(5)", [FP2]>, DwarfRegNum<[38, 17, 16]>;
|
||||
def ST6 : STRegister<"st(6)", [FP1]>, DwarfRegNum<[39, 18, 17]>;
|
||||
def ST7 : STRegister<"st(7)", [FP0]>, DwarfRegNum<[40, 19, 18]>;
|
||||
|
||||
// Floating-point status word
|
||||
def FPSW : Register<"fpsw">;
|
||||
|
||||
// Status flags register
|
||||
def EFLAGS : Register<"flags">;
|
||||
|
||||
// Segment registers
|
||||
def CS : Register<"cs">;
|
||||
def DS : Register<"ds">;
|
||||
def SS : Register<"ss">;
|
||||
def ES : Register<"es">;
|
||||
def FS : Register<"fs">;
|
||||
def GS : Register<"gs">;
|
||||
|
||||
// Debug registers
|
||||
def DR0 : Register<"dr0">;
|
||||
def DR1 : Register<"dr1">;
|
||||
def DR2 : Register<"dr2">;
|
||||
def DR3 : Register<"dr3">;
|
||||
def DR4 : Register<"dr4">;
|
||||
def DR5 : Register<"dr5">;
|
||||
def DR6 : Register<"dr6">;
|
||||
def DR7 : Register<"dr7">;
|
||||
|
||||
// Control registers
|
||||
def CR0 : Register<"cr0">;
|
||||
def CR1 : Register<"cr1">;
|
||||
def CR2 : Register<"cr2">;
|
||||
def CR3 : Register<"cr3">;
|
||||
def CR4 : Register<"cr4">;
|
||||
def CR5 : Register<"cr5">;
|
||||
def CR6 : Register<"cr6">;
|
||||
def CR7 : Register<"cr7">;
|
||||
def CR8 : Register<"cr8">;
|
||||
def CR9 : Register<"cr9">;
|
||||
def CR10 : Register<"cr10">;
|
||||
def CR11 : Register<"cr11">;
|
||||
def CR12 : Register<"cr12">;
|
||||
def CR13 : Register<"cr13">;
|
||||
def CR14 : Register<"cr14">;
|
||||
def CR15 : Register<"cr15">;
|
||||
|
||||
// Pseudo index registers
|
||||
def EIZ : Register<"eiz">;
|
||||
def RIZ : Register<"riz">;
|
||||
def sub_xmm : SubRegIndex;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Register definitions...
|
||||
//
|
||||
|
||||
// In the register alias definitions below, we define which registers alias
|
||||
// which others. We only specify which registers the small registers alias,
|
||||
// because the register file generator is smart enough to figure out that
|
||||
// AL aliases AX if we tell it that AX aliased AL (for example).
|
||||
|
||||
// Dwarf numbering is different for 32-bit and 64-bit, and there are
|
||||
// variations by target as well. Currently the first entry is for X86-64,
|
||||
// second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux
|
||||
// and debug information on X86-32/Darwin)
|
||||
|
||||
// 8-bit registers
|
||||
// Low registers
|
||||
def AL : X86Reg<"al", 0>;
|
||||
def DL : X86Reg<"dl", 2>;
|
||||
def CL : X86Reg<"cl", 1>;
|
||||
def BL : X86Reg<"bl", 3>;
|
||||
|
||||
// High registers. On x86-64, these cannot be used in any instruction
|
||||
// with a REX prefix.
|
||||
def AH : X86Reg<"ah", 4>;
|
||||
def DH : X86Reg<"dh", 6>;
|
||||
def CH : X86Reg<"ch", 5>;
|
||||
def BH : X86Reg<"bh", 7>;
|
||||
|
||||
// X86-64 only, requires REX.
|
||||
let CostPerUse = 1 in {
|
||||
def SIL : X86Reg<"sil", 6>;
|
||||
def DIL : X86Reg<"dil", 7>;
|
||||
def BPL : X86Reg<"bpl", 5>;
|
||||
def SPL : X86Reg<"spl", 4>;
|
||||
def R8B : X86Reg<"r8b", 8>;
|
||||
def R9B : X86Reg<"r9b", 9>;
|
||||
def R10B : X86Reg<"r10b", 10>;
|
||||
def R11B : X86Reg<"r11b", 11>;
|
||||
def R12B : X86Reg<"r12b", 12>;
|
||||
def R13B : X86Reg<"r13b", 13>;
|
||||
def R14B : X86Reg<"r14b", 14>;
|
||||
def R15B : X86Reg<"r15b", 15>;
|
||||
}
|
||||
|
||||
// 16-bit registers
|
||||
let SubRegIndices = [sub_8bit, sub_8bit_hi], CoveredBySubRegs = 1 in {
|
||||
def AX : X86Reg<"ax", 0, [AL,AH]>;
|
||||
def DX : X86Reg<"dx", 2, [DL,DH]>;
|
||||
def CX : X86Reg<"cx", 1, [CL,CH]>;
|
||||
def BX : X86Reg<"bx", 3, [BL,BH]>;
|
||||
}
|
||||
let SubRegIndices = [sub_8bit] in {
|
||||
def SI : X86Reg<"si", 6, [SIL]>;
|
||||
def DI : X86Reg<"di", 7, [DIL]>;
|
||||
def BP : X86Reg<"bp", 5, [BPL]>;
|
||||
def SP : X86Reg<"sp", 4, [SPL]>;
|
||||
}
|
||||
def IP : X86Reg<"ip", 0>;
|
||||
|
||||
// X86-64 only, requires REX.
|
||||
let SubRegIndices = [sub_8bit], CostPerUse = 1 in {
|
||||
def R8W : X86Reg<"r8w", 8, [R8B]>;
|
||||
def R9W : X86Reg<"r9w", 9, [R9B]>;
|
||||
def R10W : X86Reg<"r10w", 10, [R10B]>;
|
||||
def R11W : X86Reg<"r11w", 11, [R11B]>;
|
||||
def R12W : X86Reg<"r12w", 12, [R12B]>;
|
||||
def R13W : X86Reg<"r13w", 13, [R13B]>;
|
||||
def R14W : X86Reg<"r14w", 14, [R14B]>;
|
||||
def R15W : X86Reg<"r15w", 15, [R15B]>;
|
||||
}
|
||||
|
||||
// 32-bit registers
|
||||
let SubRegIndices = [sub_16bit] in {
|
||||
def EAX : X86Reg<"eax", 0, [AX]>, DwarfRegNum<[-2, 0, 0]>;
|
||||
def EDX : X86Reg<"edx", 2, [DX]>, DwarfRegNum<[-2, 2, 2]>;
|
||||
def ECX : X86Reg<"ecx", 1, [CX]>, DwarfRegNum<[-2, 1, 1]>;
|
||||
def EBX : X86Reg<"ebx", 3, [BX]>, DwarfRegNum<[-2, 3, 3]>;
|
||||
def ESI : X86Reg<"esi", 6, [SI]>, DwarfRegNum<[-2, 6, 6]>;
|
||||
def EDI : X86Reg<"edi", 7, [DI]>, DwarfRegNum<[-2, 7, 7]>;
|
||||
def EBP : X86Reg<"ebp", 5, [BP]>, DwarfRegNum<[-2, 4, 5]>;
|
||||
def ESP : X86Reg<"esp", 4, [SP]>, DwarfRegNum<[-2, 5, 4]>;
|
||||
def EIP : X86Reg<"eip", 0, [IP]>, DwarfRegNum<[-2, 8, 8]>;
|
||||
|
||||
// X86-64 only, requires REX
|
||||
let CostPerUse = 1 in {
|
||||
def R8D : X86Reg<"r8d", 8, [R8W]>;
|
||||
def R9D : X86Reg<"r9d", 9, [R9W]>;
|
||||
def R10D : X86Reg<"r10d", 10, [R10W]>;
|
||||
def R11D : X86Reg<"r11d", 11, [R11W]>;
|
||||
def R12D : X86Reg<"r12d", 12, [R12W]>;
|
||||
def R13D : X86Reg<"r13d", 13, [R13W]>;
|
||||
def R14D : X86Reg<"r14d", 14, [R14W]>;
|
||||
def R15D : X86Reg<"r15d", 15, [R15W]>;
|
||||
}}
|
||||
|
||||
// 64-bit registers, X86-64 only
|
||||
let SubRegIndices = [sub_32bit] in {
|
||||
def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>;
|
||||
def RDX : X86Reg<"rdx", 2, [EDX]>, DwarfRegNum<[1, -2, -2]>;
|
||||
def RCX : X86Reg<"rcx", 1, [ECX]>, DwarfRegNum<[2, -2, -2]>;
|
||||
def RBX : X86Reg<"rbx", 3, [EBX]>, DwarfRegNum<[3, -2, -2]>;
|
||||
def RSI : X86Reg<"rsi", 6, [ESI]>, DwarfRegNum<[4, -2, -2]>;
|
||||
def RDI : X86Reg<"rdi", 7, [EDI]>, DwarfRegNum<[5, -2, -2]>;
|
||||
def RBP : X86Reg<"rbp", 5, [EBP]>, DwarfRegNum<[6, -2, -2]>;
|
||||
def RSP : X86Reg<"rsp", 4, [ESP]>, DwarfRegNum<[7, -2, -2]>;
|
||||
|
||||
// These also require REX.
|
||||
let CostPerUse = 1 in {
|
||||
def R8 : X86Reg<"r8", 8, [R8D]>, DwarfRegNum<[ 8, -2, -2]>;
|
||||
def R9 : X86Reg<"r9", 9, [R9D]>, DwarfRegNum<[ 9, -2, -2]>;
|
||||
def R10 : X86Reg<"r10", 10, [R10D]>, DwarfRegNum<[10, -2, -2]>;
|
||||
def R11 : X86Reg<"r11", 11, [R11D]>, DwarfRegNum<[11, -2, -2]>;
|
||||
def R12 : X86Reg<"r12", 12, [R12D]>, DwarfRegNum<[12, -2, -2]>;
|
||||
def R13 : X86Reg<"r13", 13, [R13D]>, DwarfRegNum<[13, -2, -2]>;
|
||||
def R14 : X86Reg<"r14", 14, [R14D]>, DwarfRegNum<[14, -2, -2]>;
|
||||
def R15 : X86Reg<"r15", 15, [R15D]>, DwarfRegNum<[15, -2, -2]>;
|
||||
def RIP : X86Reg<"rip", 0, [EIP]>, DwarfRegNum<[16, -2, -2]>;
|
||||
}}
|
||||
|
||||
// MMX Registers. These are actually aliased to ST0 .. ST7
|
||||
def MM0 : X86Reg<"mm0", 0>, DwarfRegNum<[41, 29, 29]>;
|
||||
def MM1 : X86Reg<"mm1", 1>, DwarfRegNum<[42, 30, 30]>;
|
||||
def MM2 : X86Reg<"mm2", 2>, DwarfRegNum<[43, 31, 31]>;
|
||||
def MM3 : X86Reg<"mm3", 3>, DwarfRegNum<[44, 32, 32]>;
|
||||
def MM4 : X86Reg<"mm4", 4>, DwarfRegNum<[45, 33, 33]>;
|
||||
def MM5 : X86Reg<"mm5", 5>, DwarfRegNum<[46, 34, 34]>;
|
||||
def MM6 : X86Reg<"mm6", 6>, DwarfRegNum<[47, 35, 35]>;
|
||||
def MM7 : X86Reg<"mm7", 7>, DwarfRegNum<[48, 36, 36]>;
|
||||
|
||||
// Pseudo Floating Point registers
|
||||
def FP0 : X86Reg<"fp0", 0>;
|
||||
def FP1 : X86Reg<"fp1", 0>;
|
||||
def FP2 : X86Reg<"fp2", 0>;
|
||||
def FP3 : X86Reg<"fp3", 0>;
|
||||
def FP4 : X86Reg<"fp4", 0>;
|
||||
def FP5 : X86Reg<"fp5", 0>;
|
||||
def FP6 : X86Reg<"fp6", 0>;
|
||||
|
||||
// XMM Registers, used by the various SSE instruction set extensions.
|
||||
def XMM0: X86Reg<"xmm0", 0>, DwarfRegNum<[17, 21, 21]>;
|
||||
def XMM1: X86Reg<"xmm1", 1>, DwarfRegNum<[18, 22, 22]>;
|
||||
def XMM2: X86Reg<"xmm2", 2>, DwarfRegNum<[19, 23, 23]>;
|
||||
def XMM3: X86Reg<"xmm3", 3>, DwarfRegNum<[20, 24, 24]>;
|
||||
def XMM4: X86Reg<"xmm4", 4>, DwarfRegNum<[21, 25, 25]>;
|
||||
def XMM5: X86Reg<"xmm5", 5>, DwarfRegNum<[22, 26, 26]>;
|
||||
def XMM6: X86Reg<"xmm6", 6>, DwarfRegNum<[23, 27, 27]>;
|
||||
def XMM7: X86Reg<"xmm7", 7>, DwarfRegNum<[24, 28, 28]>;
|
||||
|
||||
// X86-64 only
|
||||
let CostPerUse = 1 in {
|
||||
def XMM8: X86Reg<"xmm8", 8>, DwarfRegNum<[25, -2, -2]>;
|
||||
def XMM9: X86Reg<"xmm9", 9>, DwarfRegNum<[26, -2, -2]>;
|
||||
def XMM10: X86Reg<"xmm10", 10>, DwarfRegNum<[27, -2, -2]>;
|
||||
def XMM11: X86Reg<"xmm11", 11>, DwarfRegNum<[28, -2, -2]>;
|
||||
def XMM12: X86Reg<"xmm12", 12>, DwarfRegNum<[29, -2, -2]>;
|
||||
def XMM13: X86Reg<"xmm13", 13>, DwarfRegNum<[30, -2, -2]>;
|
||||
def XMM14: X86Reg<"xmm14", 14>, DwarfRegNum<[31, -2, -2]>;
|
||||
def XMM15: X86Reg<"xmm15", 15>, DwarfRegNum<[32, -2, -2]>;
|
||||
} // CostPerUse
|
||||
|
||||
// YMM Registers, used by AVX instructions
|
||||
let SubRegIndices = [sub_xmm] in {
|
||||
def YMM0: X86Reg<"ymm0", 0, [XMM0]>, DwarfRegAlias<XMM0>;
|
||||
def YMM1: X86Reg<"ymm1", 1, [XMM1]>, DwarfRegAlias<XMM1>;
|
||||
def YMM2: X86Reg<"ymm2", 2, [XMM2]>, DwarfRegAlias<XMM2>;
|
||||
def YMM3: X86Reg<"ymm3", 3, [XMM3]>, DwarfRegAlias<XMM3>;
|
||||
def YMM4: X86Reg<"ymm4", 4, [XMM4]>, DwarfRegAlias<XMM4>;
|
||||
def YMM5: X86Reg<"ymm5", 5, [XMM5]>, DwarfRegAlias<XMM5>;
|
||||
def YMM6: X86Reg<"ymm6", 6, [XMM6]>, DwarfRegAlias<XMM6>;
|
||||
def YMM7: X86Reg<"ymm7", 7, [XMM7]>, DwarfRegAlias<XMM7>;
|
||||
def YMM8: X86Reg<"ymm8", 8, [XMM8]>, DwarfRegAlias<XMM8>;
|
||||
def YMM9: X86Reg<"ymm9", 9, [XMM9]>, DwarfRegAlias<XMM9>;
|
||||
def YMM10: X86Reg<"ymm10", 10, [XMM10]>, DwarfRegAlias<XMM10>;
|
||||
def YMM11: X86Reg<"ymm11", 11, [XMM11]>, DwarfRegAlias<XMM11>;
|
||||
def YMM12: X86Reg<"ymm12", 12, [XMM12]>, DwarfRegAlias<XMM12>;
|
||||
def YMM13: X86Reg<"ymm13", 13, [XMM13]>, DwarfRegAlias<XMM13>;
|
||||
def YMM14: X86Reg<"ymm14", 14, [XMM14]>, DwarfRegAlias<XMM14>;
|
||||
def YMM15: X86Reg<"ymm15", 15, [XMM15]>, DwarfRegAlias<XMM15>;
|
||||
}
|
||||
|
||||
class STRegister<string n, bits<16> Enc, list<Register> A> : X86Reg<n, Enc> {
|
||||
let Aliases = A;
|
||||
}
|
||||
|
||||
// Floating point stack registers. These don't map one-to-one to the FP
|
||||
// pseudo registers, but we still mark them as aliasing FP registers. That
|
||||
// way both kinds can be live without exceeding the stack depth. ST registers
|
||||
// are only live around inline assembly.
|
||||
def ST0 : STRegister<"st(0)", 0, []>, DwarfRegNum<[33, 12, 11]>;
|
||||
def ST1 : STRegister<"st(1)", 1, [FP6]>, DwarfRegNum<[34, 13, 12]>;
|
||||
def ST2 : STRegister<"st(2)", 2, [FP5]>, DwarfRegNum<[35, 14, 13]>;
|
||||
def ST3 : STRegister<"st(3)", 3, [FP4]>, DwarfRegNum<[36, 15, 14]>;
|
||||
def ST4 : STRegister<"st(4)", 4, [FP3]>, DwarfRegNum<[37, 16, 15]>;
|
||||
def ST5 : STRegister<"st(5)", 5, [FP2]>, DwarfRegNum<[38, 17, 16]>;
|
||||
def ST6 : STRegister<"st(6)", 6, [FP1]>, DwarfRegNum<[39, 18, 17]>;
|
||||
def ST7 : STRegister<"st(7)", 7, [FP0]>, DwarfRegNum<[40, 19, 18]>;
|
||||
|
||||
// Floating-point status word
|
||||
def FPSW : X86Reg<"fpsw", 0>;
|
||||
|
||||
// Status flags register
|
||||
def EFLAGS : X86Reg<"flags", 0>;
|
||||
|
||||
// Segment registers
|
||||
def CS : X86Reg<"cs", 1>;
|
||||
def DS : X86Reg<"ds", 3>;
|
||||
def SS : X86Reg<"ss", 2>;
|
||||
def ES : X86Reg<"es", 0>;
|
||||
def FS : X86Reg<"fs", 4>;
|
||||
def GS : X86Reg<"gs", 5>;
|
||||
|
||||
// Debug registers
|
||||
def DR0 : X86Reg<"dr0", 0>;
|
||||
def DR1 : X86Reg<"dr1", 1>;
|
||||
def DR2 : X86Reg<"dr2", 2>;
|
||||
def DR3 : X86Reg<"dr3", 3>;
|
||||
def DR4 : X86Reg<"dr4", 4>;
|
||||
def DR5 : X86Reg<"dr5", 5>;
|
||||
def DR6 : X86Reg<"dr6", 6>;
|
||||
def DR7 : X86Reg<"dr7", 7>;
|
||||
|
||||
// Control registers
|
||||
def CR0 : X86Reg<"cr0", 0>;
|
||||
def CR1 : X86Reg<"cr1", 1>;
|
||||
def CR2 : X86Reg<"cr2", 2>;
|
||||
def CR3 : X86Reg<"cr3", 3>;
|
||||
def CR4 : X86Reg<"cr4", 4>;
|
||||
def CR5 : X86Reg<"cr5", 5>;
|
||||
def CR6 : X86Reg<"cr6", 6>;
|
||||
def CR7 : X86Reg<"cr7", 7>;
|
||||
def CR8 : X86Reg<"cr8", 8>;
|
||||
def CR9 : X86Reg<"cr9", 9>;
|
||||
def CR10 : X86Reg<"cr10", 10>;
|
||||
def CR11 : X86Reg<"cr11", 11>;
|
||||
def CR12 : X86Reg<"cr12", 12>;
|
||||
def CR13 : X86Reg<"cr13", 13>;
|
||||
def CR14 : X86Reg<"cr14", 14>;
|
||||
def CR15 : X86Reg<"cr15", 15>;
|
||||
|
||||
// Pseudo index registers
|
||||
def EIZ : X86Reg<"eiz", 4>;
|
||||
def RIZ : X86Reg<"riz", 4>;
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Register Class Definitions... now that we have all of the pieces, define the
|
||||
|
|
|
|||
Loading…
Reference in New Issue