Print out immediate offset versions of PC-relative load/store instructions as [pc, #123] rather than simply #123.

llvm-svn: 140283

llvm/lib/Target/ARM/ARMInstrThumb2.td

@@ -114,12 +114,14 @@ def t2addrmode_imm12 : Operand<i32>,
 // t2ldrlabel  := imm12
 def t2ldrlabel : Operand<i32> {
   let EncoderMethod = "getAddrModeImm12OpValue";
+  let PrintMethod = "printT2LdrLabelOperand";
 }
 
 
 // ADR instruction labels.
 def t2adrlabel : Operand<i32> {
   let EncoderMethod = "getT2AdrLabelOpValue";
+  let PrintMethod = "printT2AdrLabelOperand";
 }
 
 

llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp

@@ -211,6 +211,29 @@ void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
   }
 }
 
+void ARMInstPrinter::printT2LdrLabelOperand(const MCInst *MI, unsigned OpNum,
+                                       raw_ostream &O) {
+  const MCOperand &MO1 = MI->getOperand(OpNum);
+  if (MO1.isExpr())
+    O << *MO1.getExpr();
+  else if (MO1.isImm())
+    O << "[pc, #" << MO1.getImm() << "]";
+  else
+    llvm_unreachable("Unknown LDR label operand?");
+}
+
+void ARMInstPrinter::printT2AdrLabelOperand(const MCInst *MI, unsigned OpNum,
+                                       raw_ostream &O) {
+  const MCOperand &MO1 = MI->getOperand(OpNum);
+  if (MO1.isExpr())
+    O << *MO1.getExpr();
+  else if (MO1.isImm())
+    O << "[pc, #" << MO1.getImm() << "]";
+  else
+    llvm_unreachable("Unknown LDR label operand?");
+}
+
+
 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
 // "Addressing Mode 1 - Data-processing operands" forms.  This includes:
 //    REG 0   0           - e.g. R5

llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.h

@@ -127,6 +127,8 @@ public:
   void printRotImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
 
   void printPCLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O);
+  void printT2LdrLabelOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
+  void printT2AdrLabelOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
 };
 
 } // end namespace llvm

llvm/test/MC/Disassembler/ARM/thumb-tests.txt

@@ -42,7 +42,7 @@
 # CHECK:	str	r2, [r5, r3]
 0xea 0x50
 
-# CHECK:	ldrb.w	r8, #-24
+# CHECK:	ldrb.w	r8, [pc, #-24]
 0x1f 0xf8 0x18 0x80
 
 # CHECK:	ldrd	r0, r1, [r7, #64]!

llvm/test/MC/Disassembler/ARM/thumb2.txt

@@ -649,12 +649,14 @@
 # CHECK: ldrh.w r5, [r6, #33]
 # CHECK: ldrh.w r5, [r6, #257]
 # CHECK: ldrh.w lr, [r7, #257]
+# CHECK: ldrh.w sp, [pc, #-21]
 
 0x35 0xf8 0x04 0x5c
 0x35 0x8c
 0xb6 0xf8 0x21 0x50
 0xb6 0xf8 0x01 0x51
 0xb7 0xf8 0x01 0xe1
+0x3f 0xf8 0x15 0xd0
 
 
 #------------------------------------------------------------------------------