forked from OSchip/llvm-project
[TableGen] Remove code beads
Code beads is useless since the only user, M68k, has moved on to a new encoding/decoding infrastructure.
This commit is contained in:
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b166aa833e
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f50be3d218
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@ -7,7 +7,6 @@ tablegen(LLVM M68kGenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM M68kGenRegisterBank.inc -gen-register-bank)
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tablegen(LLVM M68kGenRegisterBank.inc -gen-register-bank)
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tablegen(LLVM M68kGenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM M68kGenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM M68kGenSubtargetInfo.inc -gen-subtarget)
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tablegen(LLVM M68kGenSubtargetInfo.inc -gen-subtarget)
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tablegen(LLVM M68kGenMCCodeBeads.inc -gen-code-beads)
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tablegen(LLVM M68kGenMCCodeEmitter.inc -gen-emitter)
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tablegen(LLVM M68kGenMCCodeEmitter.inc -gen-emitter)
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tablegen(LLVM M68kGenMCPseudoLowering.inc -gen-pseudo-lowering)
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tablegen(LLVM M68kGenMCPseudoLowering.inc -gen-pseudo-lowering)
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tablegen(LLVM M68kGenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM M68kGenDAGISel.inc -gen-dag-isel)
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@ -8,7 +8,6 @@ add_tablegen(llvm-tblgen LLVM
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AsmWriterInst.cpp
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AsmWriterInst.cpp
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Attributes.cpp
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Attributes.cpp
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CallingConvEmitter.cpp
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CallingConvEmitter.cpp
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CodeBeadsGen.cpp
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CodeEmitterGen.cpp
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CodeEmitterGen.cpp
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CodeGenDAGPatterns.cpp
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CodeGenDAGPatterns.cpp
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CodeGenHwModes.cpp
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CodeGenHwModes.cpp
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@ -1,135 +0,0 @@
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//===---------- CodeBeadsGen.cpp - Code Beads Generator -------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// CodeBeads are data fields carrying auxiliary information for instructions.
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//
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// Under the hood it's simply implemented by a `bits` field (with arbitrary
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// length) in each TG instruction description, where this TG backend will
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// generate a helper function to access it.
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//
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// This is especially useful for expressing variable length encoding
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// instructions and complex addressing modes. Since in those cases each
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// instruction is usually associated with large amount of information like
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// addressing mode details used on a specific operand. Instead of retreating to
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// ad-hoc methods to figure out these information when encoding an instruction,
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// CodeBeads provide a clean table for the instruction encoder to lookup.
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//===----------------------------------------------------------------------===//
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#include "CodeGenInstruction.h"
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#include "CodeGenTarget.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenBackend.h"
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#include <vector>
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using namespace llvm;
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namespace {
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class CodeBeadsGen {
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RecordKeeper &Records;
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public:
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CodeBeadsGen(RecordKeeper &R) : Records(R) {}
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void run(raw_ostream &OS);
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};
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void CodeBeadsGen::run(raw_ostream &OS) {
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CodeGenTarget Target(Records);
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std::vector<Record *> Insts = Records.getAllDerivedDefinitions("Instruction");
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// For little-endian instruction bit encodings, reverse the bit order
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Target.reverseBitsForLittleEndianEncoding();
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ArrayRef<const CodeGenInstruction *> NumberedInstructions =
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Target.getInstructionsByEnumValue();
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// Emit function declaration
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OS << "const uint8_t *llvm::" << Target.getInstNamespace();
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OS << "::getMCInstrBeads(unsigned Opcode) {\n";
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// First, get the maximum bit length among all beads. And do some
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// simple validation
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unsigned MaxBitLength = 0;
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for (const CodeGenInstruction *CGI : NumberedInstructions) {
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Record *R = CGI->TheDef;
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if (!R->getValue("Beads"))
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continue;
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BitsInit *BI = R->getValueAsBitsInit("Beads");
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if (!BI->isComplete()) {
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PrintFatalError(R->getLoc(), "Record `" + R->getName() +
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"', bit field 'Beads' is not complete");
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}
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MaxBitLength = std::max(MaxBitLength, BI->getNumBits());
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}
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// Number of bytes
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unsigned Parts = MaxBitLength / 8;
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// Emit instruction base values
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OS << " static const uint8_t InstBits[][" << Parts << "] = {\n";
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for (const CodeGenInstruction *CGI : NumberedInstructions) {
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Record *R = CGI->TheDef;
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if (R->getValueAsString("Namespace") == "TargetOpcode" ||
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!R->getValue("Beads")) {
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OS << "\t{ 0x0 },\t// ";
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if (R->getValueAsBit("isPseudo"))
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OS << "(Pseudo) ";
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OS << R->getName() << "\n";
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continue;
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}
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BitsInit *BI = R->getValueAsBitsInit("Beads");
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// Convert to byte array:
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// [dcba] -> [a][b][c][d]
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OS << "\t{";
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for (unsigned p = 0; p < Parts; ++p) {
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unsigned Right = 8 * p;
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unsigned Left = Right + 8;
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uint8_t Value = 0;
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for (unsigned i = Right; i != Left; ++i) {
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unsigned Shift = i % 8;
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if (auto *B = dyn_cast<BitInit>(BI->getBit(i))) {
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Value |= (static_cast<uint8_t>(B->getValue()) << Shift);
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} else {
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PrintFatalError(R->getLoc(), "Record `" + R->getName() +
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"', bit 'Beads[" + Twine(i) +
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"]' is not defined");
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}
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}
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if (p)
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OS << ',';
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OS << " 0x";
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OS.write_hex(Value);
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OS << "";
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}
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OS << " }," << '\t' << "// " << R->getName() << "\n";
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}
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OS << "\t{ 0x0 }\n };\n";
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// Emit initial function code
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OS << " return InstBits[Opcode];\n"
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<< "}\n\n";
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}
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} // End anonymous namespace
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namespace llvm {
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void EmitCodeBeads(RecordKeeper &RK, raw_ostream &OS) {
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emitSourceFileHeader("Machine Code Beads", OS);
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CodeBeadsGen(RK).run(OS);
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}
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} // namespace llvm
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@ -25,7 +25,6 @@ enum ActionType {
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NullBackend,
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NullBackend,
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DumpJSON,
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DumpJSON,
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GenEmitter,
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GenEmitter,
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GenCodeBeads,
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GenRegisterInfo,
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GenRegisterInfo,
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GenInstrInfo,
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GenInstrInfo,
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GenInstrDocs,
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GenInstrDocs,
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@ -82,8 +81,6 @@ cl::opt<ActionType> Action(
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clEnumValN(DumpJSON, "dump-json",
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clEnumValN(DumpJSON, "dump-json",
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"Dump all records as machine-readable JSON"),
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"Dump all records as machine-readable JSON"),
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clEnumValN(GenEmitter, "gen-emitter", "Generate machine code emitter"),
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clEnumValN(GenEmitter, "gen-emitter", "Generate machine code emitter"),
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clEnumValN(GenCodeBeads, "gen-code-beads",
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"Generate machine code beads"),
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clEnumValN(GenRegisterInfo, "gen-register-info",
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clEnumValN(GenRegisterInfo, "gen-register-info",
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"Generate registers and register classes info"),
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"Generate registers and register classes info"),
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clEnumValN(GenInstrInfo, "gen-instr-info",
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clEnumValN(GenInstrInfo, "gen-instr-info",
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@ -164,9 +161,6 @@ bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) {
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case GenEmitter:
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case GenEmitter:
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EmitCodeEmitter(Records, OS);
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EmitCodeEmitter(Records, OS);
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break;
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break;
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case GenCodeBeads:
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EmitCodeBeads(Records, OS);
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break;
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case GenRegisterInfo:
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case GenRegisterInfo:
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EmitRegisterInfo(Records, OS);
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EmitRegisterInfo(Records, OS);
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break;
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break;
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@ -67,7 +67,6 @@ void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS);
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void EmitAsmWriter(RecordKeeper &RK, raw_ostream &OS);
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void EmitAsmWriter(RecordKeeper &RK, raw_ostream &OS);
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void EmitCallingConv(RecordKeeper &RK, raw_ostream &OS);
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void EmitCallingConv(RecordKeeper &RK, raw_ostream &OS);
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void EmitCodeEmitter(RecordKeeper &RK, raw_ostream &OS);
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void EmitCodeEmitter(RecordKeeper &RK, raw_ostream &OS);
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void EmitCodeBeads(RecordKeeper &RK, raw_ostream &OS);
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void EmitDAGISel(RecordKeeper &RK, raw_ostream &OS);
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void EmitDAGISel(RecordKeeper &RK, raw_ostream &OS);
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void EmitDFAPacketizer(RecordKeeper &RK, raw_ostream &OS);
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void EmitDFAPacketizer(RecordKeeper &RK, raw_ostream &OS);
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void EmitDisassembler(RecordKeeper &RK, raw_ostream &OS);
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void EmitDisassembler(RecordKeeper &RK, raw_ostream &OS);
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@ -12,7 +12,6 @@ executable("llvm-tblgen") {
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"Attributes.cpp",
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"Attributes.cpp",
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"CTagsEmitter.cpp",
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"CTagsEmitter.cpp",
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"CallingConvEmitter.cpp",
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"CallingConvEmitter.cpp",
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"CodeBeadsGen.cpp",
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"CodeEmitterGen.cpp",
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"CodeEmitterGen.cpp",
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"CodeGenDAGPatterns.cpp",
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"CodeGenDAGPatterns.cpp",
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"CodeGenHwModes.cpp",
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"CodeGenHwModes.cpp",
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