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R0 is a sub-register of X0, etc. 

llvm-svn: 36939
This commit is contained in:
Evan Cheng 2007-05-08 17:03:51 +00:00
parent 1c153dd152
commit f50ba31ec6
1 changed files with 3 additions and 3 deletions
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6
llvm/lib/Target/PowerPC/PPCRegisterInfo.td
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@ -22,9 +22,9 @@ class GPR<bits<5> num, string n> : PPCReg<n> {
}
// GP8 - One of the 32 64-bit general-purpose registers
class GP8<GPR Alias> : PPCReg<Alias.Name> {
field bits<5> Num = Alias.Num;
let Aliases = [Alias];
class GP8<GPR SubReg> : PPCReg<SubReg.Name> {
field bits<5> Num = SubReg.Num;
let SubRegs = [SubReg];
}
// SPR - One of the 32-bit special-purpose registers