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[IR] Move a few static functions in Instruction class inline. 

They just check for certain opcodes and opcode enums are available in Instruction.h.

llvm-svn: 298237
This commit is contained in:
Craig Topper 2017-03-20 06:40:39 +00:00
parent c69955c6f3
commit f4fa291d83
2 changed files with 17 additions and 49 deletions
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21
llvm/include/llvm/IR/Instruction.h
View File

@ -383,11 +383,20 @@ public:
///
/// Commutative operators satisfy: (x op y) === (y op x)
///
/// In LLVM, these are the associative operators, plus SetEQ and SetNE, when
/// In LLVM, these are the commutative operators, plus SetEQ and SetNE, when
/// applied to any type.
///
bool isCommutative() const { return isCommutative(getOpcode()); }
static bool isCommutative(unsigned op);
static bool isCommutative(unsigned Opcode) {
switch (Opcode) {
case Add: case FAdd:
case Mul: case FMul:
case And: case Or: case Xor:
return true;
default:
return false;
}
}
/// Return true if the instruction is idempotent:
///
@ -396,7 +405,9 @@ public:
/// In LLVM, the And and Or operators are idempotent.
///
bool isIdempotent() const { return isIdempotent(getOpcode()); }
static bool isIdempotent(unsigned op);
static bool isIdempotent(unsigned Opcode) {
return Opcode == And || Opcode == Or;
}
/// Return true if the instruction is nilpotent:
///
@ -408,7 +419,9 @@ public:
/// In LLVM, the Xor operator is nilpotent.
///
bool isNilpotent() const { return isNilpotent(getOpcode()); }
static bool isNilpotent(unsigned op);
static bool isNilpotent(unsigned Opcode) {
return Opcode == Xor;
}
/// Return true if this instruction may modify memory.
bool mayWriteToMemory() const;

45
llvm/lib/IR/Instruction.cpp
View File

@ -569,51 +569,6 @@ bool Instruction::isAssociative() const {
}
}
/// Return true if the instruction is commutative:
///
/// Commutative operators satisfy: (x op y) === (y op x)
///
/// In LLVM, these are the associative operators, plus SetEQ and SetNE, when
/// applied to any type.
///
bool Instruction::isCommutative(unsigned op) {
switch (op) {
case Add:
case FAdd:
case Mul:
case FMul:
case And:
case Or:
case Xor:
return true;
default:
return false;
}
}
/// Return true if the instruction is idempotent:
///
/// Idempotent operators satisfy: x op x === x
///
/// In LLVM, the And and Or operators are idempotent.
///
bool Instruction::isIdempotent(unsigned Opcode) {
return Opcode == And || Opcode == Or;
}
/// Return true if the instruction is nilpotent:
///
/// Nilpotent operators satisfy: x op x === Id,
///
/// where Id is the identity for the operator, i.e. a constant such that
/// x op Id === x and Id op x === x for all x.
///
/// In LLVM, the Xor operator is nilpotent.
///
bool Instruction::isNilpotent(unsigned Opcode) {
return Opcode == Xor;
}
Instruction *Instruction::cloneImpl() const {
llvm_unreachable("Subclass of Instruction failed to implement cloneImpl");
}