forked from OSchip/llvm-project
[ARM,MVE] Add InstCombine rules for pred_i2v / pred_v2i.
If you're writing C code using the ACLE MVE intrinsics that passes the result of a vcmp as input to a predicated intrinsic, e.g. mve_pred16_t pred = vcmpeqq(v1, v2); v_out = vaddq_m(v_inactive, v3, v4, pred); then clang's codegen for the compare intrinsic will create calls to `@llvm.arm.mve.pred.v2i` to convert the output of `icmp` into an `mve_pred16_t` integer representation, and then the next intrinsic will call `@llvm.arm.mve.pred.i2v` to convert it straight back again. This will be visible in the generated code as a `vmrs`/`vmsr` pair that move the predicate value pointlessly out of `p0` and back into it again. To prevent that, I've added InstCombine rules to remove round trips of the form `v2i(i2v(x))` and `i2v(v2i(x))`. Also I've taught InstCombine about the known and demanded bits of those intrinsics. As a result, you now get just the generated code you wanted: vpt.u16 eq, q1, q2 vaddt.u16 q0, q3, q4 Reviewers: ostannard, MarkMurrayARM, dmgreen Reviewed By: dmgreen Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70313
This commit is contained in:
Simon Tatham
parent
4a4dd85e5a
commit
f4f77aa53e
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@ -3308,6 +3308,34 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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}
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break;
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}
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case Intrinsic::arm_mve_pred_i2v: {
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Value *Arg = II->getArgOperand(0);
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Value *ArgArg;
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if (match(Arg, m_Intrinsic<Intrinsic::arm_mve_pred_v2i>(m_Value(ArgArg))) &&
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II->getType() == ArgArg->getType())
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return replaceInstUsesWith(*II, ArgArg);
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KnownBits ScalarKnown(32);
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if (SimplifyDemandedBits(II, 0, APInt::getLowBitsSet(32, 16),
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ScalarKnown, 0))
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return II;
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break;
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}
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case Intrinsic::arm_mve_pred_v2i: {
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Value *Arg = II->getArgOperand(0);
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Value *ArgArg;
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if (match(Arg, m_Intrinsic<Intrinsic::arm_mve_pred_i2v>(m_Value(ArgArg))))
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return replaceInstUsesWith(*II, ArgArg);
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if (!II->getMetadata(LLVMContext::MD_range)) {
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Type *IntTy32 = Type::getInt32Ty(II->getContext());
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Metadata *M[] = {
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ConstantAsMetadata::get(ConstantInt::get(IntTy32, 0)),
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ConstantAsMetadata::get(ConstantInt::get(IntTy32, 0xFFFF))
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};
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II->setMetadata(LLVMContext::MD_range, MDNode::get(II->getContext(), M));
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return II;
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}
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break;
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}
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case Intrinsic::arm_mve_vadc:
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case Intrinsic::arm_mve_vadc_predicated: {
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unsigned CarryOp =
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@ -0,0 +1,22 @@
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; RUN: opt -instcombine %s | llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve --verify-machineinstrs -o - | FileCheck %s
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define arm_aapcs_vfpcc <8 x i16> @test_vpt_block(<8 x i16> %v_inactive, <8 x i16> %v1, <8 x i16> %v2, <8 x i16> %v3) {
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; CHECK-LABEL: test_vpt_block:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vpt.i16 eq, q1, q2
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; CHECK-NEXT: vaddt.i16 q0, q3, q2
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; CHECK-NEXT: bx lr
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entry:
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%0 = icmp eq <8 x i16> %v1, %v2
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%1 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %0)
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%2 = trunc i32 %1 to i16
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%3 = zext i16 %2 to i32
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%4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
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%5 = call <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16> %v3, <8 x i16> %v2, <8 x i1> %4, <8 x i16> %v_inactive)
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ret <8 x i16> %5
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}
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declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>)
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declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)
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declare <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>)
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@ -0,0 +1,236 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -instcombine -S -o - %s | FileCheck %s
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declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>)
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declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>)
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declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>)
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declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
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declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)
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declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)
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; Round-trip conversions from predicate vector to i32 back to the same
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; size of vector should be eliminated.
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define <4 x i1> @v2i2v_4(<4 x i1> %vin) {
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; CHECK-LABEL: @v2i2v_4(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <4 x i1> [[VIN:%.*]]
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;
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entry:
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%int = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %vin)
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%vout = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %int)
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ret <4 x i1> %vout
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}
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define <8 x i1> @v2i2v_8(<8 x i1> %vin) {
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; CHECK-LABEL: @v2i2v_8(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <8 x i1> [[VIN:%.*]]
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;
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entry:
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%int = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %vin)
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%vout = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %int)
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ret <8 x i1> %vout
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}
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define <16 x i1> @v2i2v_16(<16 x i1> %vin) {
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; CHECK-LABEL: @v2i2v_16(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <16 x i1> [[VIN:%.*]]
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;
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entry:
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%int = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %vin)
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%vout = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %int)
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ret <16 x i1> %vout
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}
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; Conversions from a predicate vector to i32 and then to a _different_
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; size of predicate vector should be left alone.
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define <16 x i1> @v2i2v_4_16(<4 x i1> %vin) {
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; CHECK-LABEL: @v2i2v_4_16(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[INT:%.*]] = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> [[VIN:%.*]]), !range !0
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; CHECK-NEXT: [[VOUT:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[INT]])
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; CHECK-NEXT: ret <16 x i1> [[VOUT]]
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;
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entry:
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%int = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %vin)
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%vout = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %int)
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ret <16 x i1> %vout
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}
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define <4 x i1> @v2i2v_8_4(<8 x i1> %vin) {
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; CHECK-LABEL: @v2i2v_8_4(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[INT:%.*]] = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> [[VIN:%.*]]), !range !0
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; CHECK-NEXT: [[VOUT:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[INT]])
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; CHECK-NEXT: ret <4 x i1> [[VOUT]]
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;
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entry:
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%int = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %vin)
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%vout = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %int)
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ret <4 x i1> %vout
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}
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define <8 x i1> @v2i2v_16_8(<16 x i1> %vin) {
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; CHECK-LABEL: @v2i2v_16_8(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[INT:%.*]] = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> [[VIN:%.*]]), !range !0
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; CHECK-NEXT: [[VOUT:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[INT]])
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; CHECK-NEXT: ret <8 x i1> [[VOUT]]
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;
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entry:
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%int = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %vin)
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%vout = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %int)
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ret <8 x i1> %vout
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}
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; Round-trip conversions from i32 to predicate vector back to i32
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; should be eliminated.
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define i32 @i2v2i_4(i32 %iin) {
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; CHECK-LABEL: @i2v2i_4(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret i32 [[IIN:%.*]]
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;
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entry:
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%vec = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %iin)
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%iout = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %vec)
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ret i32 %iout
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}
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define i32 @i2v2i_8(i32 %iin) {
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; CHECK-LABEL: @i2v2i_8(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret i32 [[IIN:%.*]]
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;
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entry:
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%vec = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %iin)
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%iout = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %vec)
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ret i32 %iout
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}
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define i32 @i2v2i_16(i32 %iin) {
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; CHECK-LABEL: @i2v2i_16(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret i32 [[IIN:%.*]]
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;
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entry:
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%vec = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %iin)
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%iout = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %vec)
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ret i32 %iout
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}
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; v2i leaves the top 16 bits clear. So a trunc/zext pair applied to
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; its output, going via i16, can be completely eliminated - but not
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; one going via i8. Similarly with other methods of clearing the top
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; bits, like bitwise and.
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define i32 @v2i_truncext_i16(<4 x i1> %vin) {
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; CHECK-LABEL: @v2i_truncext_i16(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[WIDE1:%.*]] = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> [[VIN:%.*]]), !range !0
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; CHECK-NEXT: ret i32 [[WIDE1]]
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;
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entry:
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%wide1 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %vin)
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%narrow = trunc i32 %wide1 to i16
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%wide2 = zext i16 %narrow to i32
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ret i32 %wide2
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}
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define i32 @v2i_truncext_i8(<4 x i1> %vin) {
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; CHECK-LABEL: @v2i_truncext_i8(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[WIDE1:%.*]] = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> [[VIN:%.*]]), !range !0
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; CHECK-NEXT: [[WIDE2:%.*]] = and i32 [[WIDE1]], 255
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; CHECK-NEXT: ret i32 [[WIDE2]]
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;
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entry:
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%wide1 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %vin)
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%narrow = trunc i32 %wide1 to i8
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%wide2 = zext i8 %narrow to i32
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ret i32 %wide2
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}
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define i32 @v2i_and_16(<4 x i1> %vin) {
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; CHECK-LABEL: @v2i_and_16(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[WIDE1:%.*]] = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> [[VIN:%.*]]), !range !0
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; CHECK-NEXT: ret i32 [[WIDE1]]
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;
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entry:
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%wide1 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %vin)
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%wide2 = and i32 %wide1, 65535
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ret i32 %wide2
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}
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define i32 @v2i_and_15(<4 x i1> %vin) {
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; CHECK-LABEL: @v2i_and_15(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[WIDE1:%.*]] = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> [[VIN:%.*]]), !range !0
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; CHECK-NEXT: [[WIDE2:%.*]] = and i32 [[WIDE1]], 32767
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; CHECK-NEXT: ret i32 [[WIDE2]]
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;
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entry:
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%wide1 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %vin)
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%wide2 = and i32 %wide1, 32767
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ret i32 %wide2
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}
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; i2v doesn't use the top bits of its input. So the same operations
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; on a value that's about to be passed to i2v can be eliminated.
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define <4 x i1> @i2v_truncext_i16(i32 %wide1) {
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; CHECK-LABEL: @i2v_truncext_i16(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[VOUT:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[WIDE1:%.*]])
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; CHECK-NEXT: ret <4 x i1> [[VOUT]]
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;
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entry:
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%narrow = trunc i32 %wide1 to i16
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%wide2 = zext i16 %narrow to i32
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%vout = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %wide2)
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ret <4 x i1> %vout
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}
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define <4 x i1> @i2v_truncext_i8(i32 %wide1) {
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; CHECK-LABEL: @i2v_truncext_i8(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[WIDE2:%.*]] = and i32 [[WIDE1:%.*]], 255
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; CHECK-NEXT: [[VOUT:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[WIDE2]])
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; CHECK-NEXT: ret <4 x i1> [[VOUT]]
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;
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entry:
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%narrow = trunc i32 %wide1 to i8
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%wide2 = zext i8 %narrow to i32
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%vout = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %wide2)
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ret <4 x i1> %vout
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}
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define <4 x i1> @i2v_and_16(i32 %wide1) {
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; CHECK-LABEL: @i2v_and_16(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[VOUT:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[WIDE1:%.*]])
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; CHECK-NEXT: ret <4 x i1> [[VOUT]]
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;
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entry:
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%wide2 = and i32 %wide1, 65535
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%vout = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %wide2)
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ret <4 x i1> %vout
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}
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define <4 x i1> @i2v_and_15(i32 %wide1) {
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; CHECK-LABEL: @i2v_and_15(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[WIDE2:%.*]] = and i32 [[WIDE1:%.*]], 32767
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; CHECK-NEXT: [[VOUT:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[WIDE2]])
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; CHECK-NEXT: ret <4 x i1> [[VOUT]]
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;
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entry:
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%wide2 = and i32 %wide1, 32767
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%vout = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %wide2)
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ret <4 x i1> %vout
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}
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