forked from OSchip/llvm-project
parent
33134fa75f
commit
f4f04107ef
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@ -259,11 +259,6 @@ public:
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/// machine basic block (i.e., copies all the successors fromMBB and
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/// remove all the successors from fromMBB).
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void transferSuccessors(MachineBasicBlock *fromMBB);
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/// transferSuccessorsAndUpdatePHIs - Transfers all the successors, as
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/// in transferSuccessors, and update PHI operands in the successor blocks
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/// which refer to fromMBB to refer to this.
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void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB);
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/// isSuccessor - Return true if the specified MBB is a successor of this
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/// block.
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@ -335,32 +335,12 @@ void MachineBasicBlock::transferSuccessors(MachineBasicBlock *fromMBB) {
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if (this == fromMBB)
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return;
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while (!fromMBB->succ_empty()) {
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MachineBasicBlock *Succ = *fromMBB->succ_begin();
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addSuccessor(Succ);
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fromMBB->removeSuccessor(Succ);
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}
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}
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void
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MachineBasicBlock::transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB) {
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if (this == fromMBB)
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return;
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for (MachineBasicBlock::succ_iterator I = fromMBB->succ_begin(),
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E = fromMBB->succ_end(); I != E; ++I)
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addSuccessor(*I);
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while (!fromMBB->succ_empty()) {
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MachineBasicBlock *Succ = *fromMBB->succ_begin();
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addSuccessor(Succ);
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fromMBB->removeSuccessor(Succ);
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// Fix up any PHI nodes in the successor.
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for (MachineBasicBlock::iterator MI = Succ->begin(), ME = Succ->end();
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MI != ME && MI->isPHI(); ++MI)
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for (unsigned i = 2, e = MI->getNumOperands()+1; i != e; i += 2) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.getMBB() == fromMBB)
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MO.setMBB(this);
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}
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}
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while (!fromMBB->succ_empty())
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fromMBB->removeSuccessor(fromMBB->succ_begin());
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}
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bool MachineBasicBlock::isSuccessor(const MachineBasicBlock *MBB) const {
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@ -3637,12 +3637,7 @@ ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
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MF->insert(It, loop1MBB);
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MF->insert(It, loop2MBB);
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MF->insert(It, exitMBB);
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// Transfer the remainder of BB and its successor edges to exitMBB.
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exitMBB->splice(exitMBB->begin(), BB,
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llvm::next(MachineBasicBlock::iterator(MI)),
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BB->end());
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exitMBB->transferSuccessorsAndUpdatePHIs(BB);
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exitMBB->transferSuccessors(BB);
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// thisMBB:
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// ...
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@ -3680,7 +3675,7 @@ ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
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// ...
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BB = exitMBB;
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MI->eraseFromParent(); // The instruction is gone now.
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MF->DeleteMachineInstr(MI); // The instruction is gone now.
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return BB;
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}
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@ -3723,12 +3718,7 @@ ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
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MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MF->insert(It, loopMBB);
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MF->insert(It, exitMBB);
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// Transfer the remainder of BB and its successor edges to exitMBB.
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exitMBB->splice(exitMBB->begin(), BB,
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llvm::next(MachineBasicBlock::iterator(MI)),
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BB->end());
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exitMBB->transferSuccessorsAndUpdatePHIs(BB);
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exitMBB->transferSuccessors(BB);
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MachineRegisterInfo &RegInfo = MF->getRegInfo();
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unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
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@ -3773,7 +3763,7 @@ ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
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// ...
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BB = exitMBB;
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MI->eraseFromParent(); // The instruction is gone now.
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MF->DeleteMachineInstr(MI); // The instruction is gone now.
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return BB;
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}
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@ -3858,20 +3848,21 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineFunction *F = BB->getParent();
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MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
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F->insert(It, copy0MBB);
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F->insert(It, sinkMBB);
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// Transfer the remainder of BB and its successor edges to sinkMBB.
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sinkMBB->splice(sinkMBB->begin(), BB,
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llvm::next(MachineBasicBlock::iterator(MI)),
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BB->end());
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sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
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BB->addSuccessor(copy0MBB);
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BB->addSuccessor(sinkMBB);
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BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
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.addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
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F->insert(It, copy0MBB);
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F->insert(It, sinkMBB);
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// Update machine-CFG edges by first adding all successors of the current
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// block to the new block which will contain the Phi node for the select.
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for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
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E = BB->succ_end(); I != E; ++I)
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sinkMBB->addSuccessor(*I);
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// Next, remove all successors of the current block, and add the true
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// and fallthrough blocks as its successors.
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while (!BB->succ_empty())
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BB->removeSuccessor(BB->succ_begin());
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BB->addSuccessor(copy0MBB);
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BB->addSuccessor(sinkMBB);
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// copy0MBB:
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// %FalseValue = ...
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@ -3885,12 +3876,11 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
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// ...
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BB = sinkMBB;
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BuildMI(*BB, BB->begin(), dl,
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TII->get(ARM::PHI), MI->getOperand(0).getReg())
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BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
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.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
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MI->eraseFromParent(); // The pseudo instruction is gone now.
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F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
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return BB;
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}
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@ -3911,7 +3901,7 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg);
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unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
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? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr;
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BuildMI(*BB, MI, dl, TII->get(CopyOpc), ARM::SP)
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BuildMI(BB, dl, TII->get(CopyOpc), ARM::SP)
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.addReg(SrcReg, getKillRegState(SrcIsKill));
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}
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@ -3943,7 +3933,7 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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NeedPred = true; NeedCC = true; NeedOp3 = true;
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break;
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}
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MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(OpOpc), ARM::SP);
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MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(OpOpc), ARM::SP);
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if (OpOpc == ARM::tAND)
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AddDefaultT1CC(MIB);
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MIB.addReg(ARM::SP);
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@ -3959,10 +3949,10 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg);
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unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
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? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr;
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BuildMI(*BB, MI, dl, TII->get(CopyOpc))
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BuildMI(BB, dl, TII->get(CopyOpc))
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.addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
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.addReg(ARM::SP);
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MI->eraseFromParent(); // The pseudo instruction is gone now.
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MF->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
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return BB;
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}
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}
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@ -863,10 +863,7 @@ AlphaTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *llscMBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
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sinkMBB->splice(sinkMBB->begin(), thisMBB,
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llvm::next(MachineBasicBlock::iterator(MI)),
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thisMBB->end());
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sinkMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
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sinkMBB->transferSuccessors(thisMBB);
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F->insert(It, llscMBB);
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F->insert(It, sinkMBB);
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@ -915,7 +912,7 @@ AlphaTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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thisMBB->addSuccessor(llscMBB);
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llscMBB->addSuccessor(llscMBB);
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llscMBB->addSuccessor(sinkMBB);
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MI->eraseFromParent(); // The pseudo instruction is gone now.
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F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
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return sinkMBB;
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}
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@ -234,24 +234,6 @@ MBlazeTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineRegisterInfo &R = F->getRegInfo();
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MachineBasicBlock *loop = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *finish = F->CreateMachineBasicBlock(LLVM_BB);
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F->insert(It, loop);
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F->insert(It, finish);
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// Update machine-CFG edges by transfering adding all successors and
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// remaining instructions from the current block to the new block which
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// will contain the Phi node for the select.
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finish->splice(finish->begin(), BB,
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llvm::next(MachineBasicBlock::iterator(MI)),
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BB->end());
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finish->transferSuccessorsAndUpdatePHIs(BB);
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// Add the true and fallthrough blocks as its successors.
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BB->addSuccessor(loop);
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BB->addSuccessor(finish);
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// Next, add the finish block as a successor of the loop block
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loop->addSuccessor(finish);
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loop->addSuccessor(loop);
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unsigned IAMT = R.createVirtualRegister(MBlaze::CPURegsRegisterClass);
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BuildMI(BB, dl, TII->get(MBlaze::ANDI), IAMT)
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@ -267,6 +249,26 @@ MBlazeTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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.addReg(IAMT)
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.addMBB(finish);
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F->insert(It, loop);
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F->insert(It, finish);
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// Update machine-CFG edges by first adding all successors of the current
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// block to the new block which will contain the Phi node for the select.
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for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
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e = BB->succ_end(); i != e; ++i)
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finish->addSuccessor(*i);
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// Next, remove all successors of the current block, and add the true
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// and fallthrough blocks as its successors.
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while(!BB->succ_empty())
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BB->removeSuccessor(BB->succ_begin());
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BB->addSuccessor(loop);
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BB->addSuccessor(finish);
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// Next, add the finish block as a successor of the loop block
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loop->addSuccessor(finish);
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loop->addSuccessor(loop);
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unsigned DST = R.createVirtualRegister(MBlaze::CPURegsRegisterClass);
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unsigned NDST = R.createVirtualRegister(MBlaze::CPURegsRegisterClass);
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BuildMI(loop, dl, TII->get(MBlaze::PHI), DST)
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@ -296,13 +298,12 @@ MBlazeTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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.addReg(NAMT)
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.addMBB(loop);
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BuildMI(*finish, finish->begin(), dl,
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TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
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BuildMI(finish, dl, TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
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.addReg(IVAL).addMBB(BB)
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.addReg(NDST).addMBB(loop);
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// The pseudo instruction is no longer needed so remove it
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MI->eraseFromParent();
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F->DeleteMachineInstr(MI);
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return finish;
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}
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@ -337,23 +338,27 @@ MBlazeTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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case MBlazeCC::LE: Opc = MBlaze::BGTID; break;
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}
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F->insert(It, flsBB);
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F->insert(It, dneBB);
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// Transfer the remainder of BB and its successor edges to dneBB.
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dneBB->splice(dneBB->begin(), BB,
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llvm::next(MachineBasicBlock::iterator(MI)),
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BB->end());
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dneBB->transferSuccessorsAndUpdatePHIs(BB);
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BB->addSuccessor(flsBB);
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BB->addSuccessor(dneBB);
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flsBB->addSuccessor(dneBB);
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BuildMI(BB, dl, TII->get(Opc))
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.addReg(MI->getOperand(3).getReg())
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.addMBB(dneBB);
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F->insert(It, flsBB);
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F->insert(It, dneBB);
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// Update machine-CFG edges by first adding all successors of the current
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// block to the new block which will contain the Phi node for the select.
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for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
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e = BB->succ_end(); i != e; ++i)
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dneBB->addSuccessor(*i);
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// Next, remove all successors of the current block, and add the true
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// and fallthrough blocks as its successors.
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while(!BB->succ_empty())
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BB->removeSuccessor(BB->succ_begin());
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BB->addSuccessor(flsBB);
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BB->addSuccessor(dneBB);
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flsBB->addSuccessor(dneBB);
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// sinkMBB:
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// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
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// ...
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@ -361,12 +366,11 @@ MBlazeTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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// .addReg(MI->getOperand(1).getReg()).addMBB(flsBB)
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// .addReg(MI->getOperand(2).getReg()).addMBB(BB);
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BuildMI(*dneBB, dneBB->begin(), dl,
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TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
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BuildMI(dneBB, dl, TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
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.addReg(MI->getOperand(2).getReg()).addMBB(flsBB)
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.addReg(MI->getOperand(1).getReg()).addMBB(BB);
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MI->eraseFromParent(); // The pseudo instruction is gone now.
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F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
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return dneBB;
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}
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}
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@ -1070,10 +1070,7 @@ MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,
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// Update machine-CFG edges by transferring all successors of the current
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// block to the block containing instructions after shift.
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RemBB->splice(RemBB->begin(), BB,
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llvm::next(MachineBasicBlock::iterator(MI)),
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BB->end());
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RemBB->transferSuccessorsAndUpdatePHIs(BB);
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RemBB->transferSuccessors(BB);
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// Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
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BB->addSuccessor(LoopBB);
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@ -1119,11 +1116,11 @@ MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,
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// RemBB:
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// DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
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BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
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BuildMI(RemBB, dl, TII.get(MSP430::PHI), DstReg)
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.addReg(SrcReg).addMBB(BB)
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.addReg(ShiftReg2).addMBB(LoopBB);
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MI->eraseFromParent(); // The pseudo instruction is gone now.
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F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
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return RemBB;
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}
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@ -1161,22 +1158,18 @@ MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineFunction *F = BB->getParent();
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MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
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BuildMI(BB, dl, TII.get(MSP430::JCC))
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.addMBB(copy1MBB)
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.addImm(MI->getOperand(3).getImm());
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F->insert(I, copy0MBB);
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F->insert(I, copy1MBB);
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// Update machine-CFG edges by transferring all successors of the current
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// block to the new block which will contain the Phi node for the select.
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copy1MBB->splice(copy1MBB->begin(), BB,
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llvm::next(MachineBasicBlock::iterator(MI)),
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BB->end());
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copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
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copy1MBB->transferSuccessors(BB);
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// Next, add the true and fallthrough blocks as its successors.
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BB->addSuccessor(copy0MBB);
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BB->addSuccessor(copy1MBB);
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BuildMI(BB, dl, TII.get(MSP430::JCC))
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.addMBB(copy1MBB)
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.addImm(MI->getOperand(3).getImm());
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// copy0MBB:
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// %FalseValue = ...
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// # fallthrough to copy1MBB
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@ -1189,11 +1182,11 @@ MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
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// ...
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BB = copy1MBB;
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BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI),
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BuildMI(BB, dl, TII.get(MSP430::PHI),
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MI->getOperand(0).getReg())
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.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
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.addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
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MI->eraseFromParent(); // The pseudo instruction is gone now.
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F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
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return BB;
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}
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@ -284,18 +284,6 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineFunction *F = BB->getParent();
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MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
||||
F->insert(It, copy0MBB);
|
||||
F->insert(It, sinkMBB);
|
||||
|
||||
// Transfer the remainder of BB and its successor edges to sinkMBB.
|
||||
sinkMBB->splice(sinkMBB->begin(), BB,
|
||||
llvm::next(MachineBasicBlock::iterator(MI)),
|
||||
BB->end());
|
||||
sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
|
||||
|
||||
// Next, add the true and fallthrough blocks as its successors.
|
||||
BB->addSuccessor(copy0MBB);
|
||||
BB->addSuccessor(sinkMBB);
|
||||
|
||||
// Emit the right instruction according to the type of the operands compared
|
||||
if (isFPCmp) {
|
||||
|
@ -308,6 +296,20 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|||
BuildMI(BB, dl, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
|
||||
.addReg(Mips::ZERO).addMBB(sinkMBB);
|
||||
|
||||
F->insert(It, copy0MBB);
|
||||
F->insert(It, sinkMBB);
|
||||
// Update machine-CFG edges by first adding all successors of the current
|
||||
// block to the new block which will contain the Phi node for the select.
|
||||
for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
|
||||
e = BB->succ_end(); i != e; ++i)
|
||||
sinkMBB->addSuccessor(*i);
|
||||
// Next, remove all successors of the current block, and add the true
|
||||
// and fallthrough blocks as its successors.
|
||||
while(!BB->succ_empty())
|
||||
BB->removeSuccessor(BB->succ_begin());
|
||||
BB->addSuccessor(copy0MBB);
|
||||
BB->addSuccessor(sinkMBB);
|
||||
|
||||
// copy0MBB:
|
||||
// %FalseValue = ...
|
||||
// # fallthrough to sinkMBB
|
||||
|
@ -320,12 +322,11 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|||
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
|
||||
// ...
|
||||
BB = sinkMBB;
|
||||
BuildMI(*BB, BB->begin(), dl,
|
||||
TII->get(Mips::PHI), MI->getOperand(0).getReg())
|
||||
BuildMI(BB, dl, TII->get(Mips::PHI), MI->getOperand(0).getReg())
|
||||
.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
|
||||
.addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
|
||||
|
||||
MI->eraseFromParent(); // The pseudo instruction is gone now.
|
||||
F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
|
||||
return BB;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -1928,12 +1928,15 @@ PIC16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|||
F->insert(It, copy0MBB);
|
||||
F->insert(It, sinkMBB);
|
||||
|
||||
// Transfer the remainder of BB and its successor edges to sinkMBB.
|
||||
sinkMBB->splice(sinkMBB->begin(), BB,
|
||||
llvm::next(MachineBasicBlock::iterator(MI)),
|
||||
BB->end());
|
||||
sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
|
||||
|
||||
// Update machine-CFG edges by first adding all successors of the current
|
||||
// block to the new block which will contain the Phi node for the select.
|
||||
for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
|
||||
E = BB->succ_end(); I != E; ++I)
|
||||
sinkMBB->addSuccessor(*I);
|
||||
// Next, remove all successors of the current block, and add the true
|
||||
// and fallthrough blocks as its successors.
|
||||
while (!BB->succ_empty())
|
||||
BB->removeSuccessor(BB->succ_begin());
|
||||
// Next, add the true and fallthrough blocks as its successors.
|
||||
BB->addSuccessor(copy0MBB);
|
||||
BB->addSuccessor(sinkMBB);
|
||||
|
@ -1950,12 +1953,11 @@ PIC16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|||
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
|
||||
// ...
|
||||
BB = sinkMBB;
|
||||
BuildMI(*BB, BB->begin(), dl,
|
||||
TII.get(PIC16::PHI), MI->getOperand(0).getReg())
|
||||
BuildMI(BB, dl, TII.get(PIC16::PHI), MI->getOperand(0).getReg())
|
||||
.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
|
||||
.addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
|
||||
|
||||
MI->eraseFromParent(); // The pseudo instruction is gone now.
|
||||
F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
|
||||
return BB;
|
||||
}
|
||||
|
||||
|
|
|
@ -4513,10 +4513,7 @@ PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
|
|||
MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
||||
F->insert(It, loopMBB);
|
||||
F->insert(It, exitMBB);
|
||||
exitMBB->splice(exitMBB->begin(), BB,
|
||||
llvm::next(MachineBasicBlock::iterator(MI)),
|
||||
BB->end());
|
||||
exitMBB->transferSuccessorsAndUpdatePHIs(BB);
|
||||
exitMBB->transferSuccessors(BB);
|
||||
|
||||
MachineRegisterInfo &RegInfo = F->getRegInfo();
|
||||
unsigned TmpReg = (!BinOpcode) ? incr :
|
||||
|
@ -4581,10 +4578,7 @@ PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
|
|||
MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
||||
F->insert(It, loopMBB);
|
||||
F->insert(It, exitMBB);
|
||||
exitMBB->splice(exitMBB->begin(), BB,
|
||||
llvm::next(MachineBasicBlock::iterator(MI)),
|
||||
BB->end());
|
||||
exitMBB->transferSuccessorsAndUpdatePHIs(BB);
|
||||
exitMBB->transferSuccessors(BB);
|
||||
|
||||
MachineRegisterInfo &RegInfo = F->getRegInfo();
|
||||
const TargetRegisterClass *RC =
|
||||
|
@ -4717,22 +4711,23 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|||
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
||||
unsigned SelectPred = MI->getOperand(4).getImm();
|
||||
DebugLoc dl = MI->getDebugLoc();
|
||||
BuildMI(BB, dl, TII->get(PPC::BCC))
|
||||
.addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
|
||||
F->insert(It, copy0MBB);
|
||||
F->insert(It, sinkMBB);
|
||||
|
||||
// Transfer the remainder of BB and its successor edges to sinkMBB.
|
||||
sinkMBB->splice(sinkMBB->begin(), BB,
|
||||
llvm::next(MachineBasicBlock::iterator(MI)),
|
||||
BB->end());
|
||||
sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
|
||||
|
||||
// Update machine-CFG edges by first adding all successors of the current
|
||||
// block to the new block which will contain the Phi node for the select.
|
||||
for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
|
||||
E = BB->succ_end(); I != E; ++I)
|
||||
sinkMBB->addSuccessor(*I);
|
||||
// Next, remove all successors of the current block, and add the true
|
||||
// and fallthrough blocks as its successors.
|
||||
while (!BB->succ_empty())
|
||||
BB->removeSuccessor(BB->succ_begin());
|
||||
// Next, add the true and fallthrough blocks as its successors.
|
||||
BB->addSuccessor(copy0MBB);
|
||||
BB->addSuccessor(sinkMBB);
|
||||
|
||||
BuildMI(BB, dl, TII->get(PPC::BCC))
|
||||
.addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
|
||||
|
||||
// copy0MBB:
|
||||
// %FalseValue = ...
|
||||
// # fallthrough to sinkMBB
|
||||
|
@ -4745,8 +4740,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|||
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
|
||||
// ...
|
||||
BB = sinkMBB;
|
||||
BuildMI(*BB, BB->begin(), dl,
|
||||
TII->get(PPC::PHI), MI->getOperand(0).getReg())
|
||||
BuildMI(BB, dl, TII->get(PPC::PHI), MI->getOperand(0).getReg())
|
||||
.addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
|
||||
.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
|
||||
}
|
||||
|
@ -4832,10 +4826,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|||
F->insert(It, loop2MBB);
|
||||
F->insert(It, midMBB);
|
||||
F->insert(It, exitMBB);
|
||||
exitMBB->splice(exitMBB->begin(), BB,
|
||||
llvm::next(MachineBasicBlock::iterator(MI)),
|
||||
BB->end());
|
||||
exitMBB->transferSuccessorsAndUpdatePHIs(BB);
|
||||
exitMBB->transferSuccessors(BB);
|
||||
|
||||
// thisMBB:
|
||||
// ...
|
||||
|
@ -4903,10 +4894,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|||
F->insert(It, loop2MBB);
|
||||
F->insert(It, midMBB);
|
||||
F->insert(It, exitMBB);
|
||||
exitMBB->splice(exitMBB->begin(), BB,
|
||||
llvm::next(MachineBasicBlock::iterator(MI)),
|
||||
BB->end());
|
||||
exitMBB->transferSuccessorsAndUpdatePHIs(BB);
|
||||
exitMBB->transferSuccessors(BB);
|
||||
|
||||
MachineRegisterInfo &RegInfo = F->getRegInfo();
|
||||
const TargetRegisterClass *RC =
|
||||
|
@ -5032,7 +5020,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|||
llvm_unreachable("Unexpected instr type to insert");
|
||||
}
|
||||
|
||||
MI->eraseFromParent(); // The pseudo instruction is gone now.
|
||||
F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
|
||||
return BB;
|
||||
}
|
||||
|
||||
|
|
|
@ -1007,20 +1007,21 @@ SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|||
MachineFunction *F = BB->getParent();
|
||||
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
|
||||
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
||||
|
||||
// Transfer the remainder of BB and its successor edges to sinkMBB.
|
||||
sinkMBB->splice(sinkMBB->begin(), BB,
|
||||
llvm::next(MachineBasicBlock::iterator(MI)),
|
||||
BB->end());
|
||||
sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
|
||||
|
||||
// Add the true and fallthrough blocks as its successors.
|
||||
BB->addSuccessor(copy0MBB);
|
||||
BB->addSuccessor(sinkMBB);
|
||||
|
||||
BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
|
||||
F->insert(It, copy0MBB);
|
||||
F->insert(It, sinkMBB);
|
||||
// Update machine-CFG edges by first adding all successors of the current
|
||||
// block to the new block which will contain the Phi node for the select.
|
||||
for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
|
||||
E = BB->succ_end(); I != E; ++I)
|
||||
sinkMBB->addSuccessor(*I);
|
||||
// Next, remove all successors of the current block, and add the true
|
||||
// and fallthrough blocks as its successors.
|
||||
while (!BB->succ_empty())
|
||||
BB->removeSuccessor(BB->succ_begin());
|
||||
// Next, add the true and fallthrough blocks as its successors.
|
||||
BB->addSuccessor(copy0MBB);
|
||||
BB->addSuccessor(sinkMBB);
|
||||
|
||||
// copy0MBB:
|
||||
// %FalseValue = ...
|
||||
|
@ -1034,11 +1035,11 @@ SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|||
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
|
||||
// ...
|
||||
BB = sinkMBB;
|
||||
BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
|
||||
BuildMI(BB, dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
|
||||
.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
|
||||
.addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
|
||||
|
||||
MI->eraseFromParent(); // The pseudo instruction is gone now.
|
||||
F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
|
||||
return BB;
|
||||
}
|
||||
|
||||
|
|
|
@ -827,20 +827,16 @@ SystemZTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|||
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
|
||||
MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
|
||||
SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm();
|
||||
BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB);
|
||||
F->insert(I, copy0MBB);
|
||||
F->insert(I, copy1MBB);
|
||||
// Update machine-CFG edges by transferring all successors of the current
|
||||
// block to the new block which will contain the Phi node for the select.
|
||||
copy1MBB->splice(copy1MBB->begin(), BB,
|
||||
llvm::next(MachineBasicBlock::iterator(MI)),
|
||||
BB->end());
|
||||
copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
|
||||
copy1MBB->transferSuccessors(BB);
|
||||
// Next, add the true and fallthrough blocks as its successors.
|
||||
BB->addSuccessor(copy0MBB);
|
||||
BB->addSuccessor(copy1MBB);
|
||||
|
||||
BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB);
|
||||
|
||||
// copy0MBB:
|
||||
// %FalseValue = ...
|
||||
// # fallthrough to copy1MBB
|
||||
|
@ -853,11 +849,11 @@ SystemZTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|||
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
|
||||
// ...
|
||||
BB = copy1MBB;
|
||||
BuildMI(*BB, BB->begin(), dl, TII.get(SystemZ::PHI),
|
||||
BuildMI(BB, dl, TII.get(SystemZ::PHI),
|
||||
MI->getOperand(0).getReg())
|
||||
.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
|
||||
.addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
|
||||
|
||||
MI->eraseFromParent(); // The pseudo instruction is gone now.
|
||||
F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
|
||||
return BB;
|
||||
}
|
||||
|
|
|
@ -8023,11 +8023,8 @@ X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
|
|||
F->insert(MBBIter, newMBB);
|
||||
F->insert(MBBIter, nextMBB);
|
||||
|
||||
// Transfer the remainder of thisMBB and its successor edges to nextMBB.
|
||||
nextMBB->splice(nextMBB->begin(), thisMBB,
|
||||
llvm::next(MachineBasicBlock::iterator(bInstr)),
|
||||
thisMBB->end());
|
||||
nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
|
||||
// Move all successors to thisMBB to nextMBB
|
||||
nextMBB->transferSuccessors(thisMBB);
|
||||
|
||||
// Update thisMBB to fall through to newMBB
|
||||
thisMBB->addSuccessor(newMBB);
|
||||
|
@ -8090,7 +8087,7 @@ X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
|
|||
// insert branch
|
||||
BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
|
||||
|
||||
bInstr->eraseFromParent(); // The pseudo instruction is gone now.
|
||||
F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
|
||||
return nextMBB;
|
||||
}
|
||||
|
||||
|
@ -8135,11 +8132,8 @@ X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
|
|||
F->insert(MBBIter, newMBB);
|
||||
F->insert(MBBIter, nextMBB);
|
||||
|
||||
// Transfer the remainder of thisMBB and its successor edges to nextMBB.
|
||||
nextMBB->splice(nextMBB->begin(), thisMBB,
|
||||
llvm::next(MachineBasicBlock::iterator(bInstr)),
|
||||
thisMBB->end());
|
||||
nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
|
||||
// Move all successors to thisMBB to nextMBB
|
||||
nextMBB->transferSuccessors(thisMBB);
|
||||
|
||||
// Update thisMBB to fall through to newMBB
|
||||
thisMBB->addSuccessor(newMBB);
|
||||
|
@ -8256,7 +8250,7 @@ X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
|
|||
// insert branch
|
||||
BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
|
||||
|
||||
bInstr->eraseFromParent(); // The pseudo instruction is gone now.
|
||||
F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
|
||||
return nextMBB;
|
||||
}
|
||||
|
||||
|
@ -8290,11 +8284,8 @@ X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
|
|||
F->insert(MBBIter, newMBB);
|
||||
F->insert(MBBIter, nextMBB);
|
||||
|
||||
// Transfer the remainder of thisMBB and its successor edges to nextMBB.
|
||||
nextMBB->splice(nextMBB->begin(), thisMBB,
|
||||
llvm::next(MachineBasicBlock::iterator(mInstr)),
|
||||
thisMBB->end());
|
||||
nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
|
||||
// Move all successors of thisMBB to nextMBB
|
||||
nextMBB->transferSuccessors(thisMBB);
|
||||
|
||||
// Update thisMBB to fall through to newMBB
|
||||
thisMBB->addSuccessor(newMBB);
|
||||
|
@ -8362,7 +8353,7 @@ X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
|
|||
// insert branch
|
||||
BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
|
||||
|
||||
mInstr->eraseFromParent(); // The pseudo instruction is gone now.
|
||||
F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
|
||||
return nextMBB;
|
||||
}
|
||||
|
||||
|
@ -8372,6 +8363,7 @@ MachineBasicBlock *
|
|||
X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
|
||||
unsigned numArgs, bool memArg) const {
|
||||
|
||||
MachineFunction *F = BB->getParent();
|
||||
DebugLoc dl = MI->getDebugLoc();
|
||||
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
||||
|
||||
|
@ -8393,7 +8385,7 @@ X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
|
|||
BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
|
||||
.addReg(X86::XMM0);
|
||||
|
||||
MI->eraseFromParent();
|
||||
F->DeleteMachineInstr(MI);
|
||||
|
||||
return BB;
|
||||
}
|
||||
|
@ -8422,12 +8414,9 @@ X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
|
|||
F->insert(MBBIter, XMMSaveMBB);
|
||||
F->insert(MBBIter, EndMBB);
|
||||
|
||||
// Transfer the remainder of MBB and its successor edges to EndMBB.
|
||||
EndMBB->splice(EndMBB->begin(), MBB,
|
||||
llvm::next(MachineBasicBlock::iterator(MI)),
|
||||
MBB->end());
|
||||
EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
|
||||
|
||||
// Set up the CFG.
|
||||
// Move any original successors of MBB to the end block.
|
||||
EndMBB->transferSuccessors(MBB);
|
||||
// The original block will now fall through to the XMM save block.
|
||||
MBB->addSuccessor(XMMSaveMBB);
|
||||
// The XMMSaveMBB will fall through to the end block.
|
||||
|
@ -8466,7 +8455,7 @@ X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
|
|||
.addMemOperand(MMO);
|
||||
}
|
||||
|
||||
MI->eraseFromParent(); // The pseudo instruction is gone now.
|
||||
F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
|
||||
|
||||
return EndMBB;
|
||||
}
|
||||
|
@ -8495,17 +8484,37 @@ X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
|
|||
MachineFunction *F = BB->getParent();
|
||||
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
|
||||
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
||||
unsigned Opc =
|
||||
X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
|
||||
|
||||
BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
|
||||
F->insert(It, copy0MBB);
|
||||
F->insert(It, sinkMBB);
|
||||
|
||||
// Update machine-CFG edges by first adding all successors of the current
|
||||
// block to the new block which will contain the Phi node for the select.
|
||||
for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
|
||||
E = BB->succ_end(); I != E; ++I)
|
||||
sinkMBB->addSuccessor(*I);
|
||||
|
||||
// Next, remove all successors of the current block, and add the true
|
||||
// and fallthrough blocks as its successors.
|
||||
while (!BB->succ_empty())
|
||||
BB->removeSuccessor(BB->succ_begin());
|
||||
|
||||
// Add the true and fallthrough blocks as its successors.
|
||||
BB->addSuccessor(copy0MBB);
|
||||
BB->addSuccessor(sinkMBB);
|
||||
|
||||
// If the EFLAGS register isn't dead in the terminator, then claim that it's
|
||||
// live into the sink and copy blocks.
|
||||
const MachineFunction *MF = BB->getParent();
|
||||
const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
|
||||
BitVector ReservedRegs = TRI->getReservedRegs(*MF);
|
||||
const MachineInstr *Term = BB->getFirstTerminator();
|
||||
|
||||
for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
|
||||
const MachineOperand &MO = MI->getOperand(I);
|
||||
for (unsigned I = 0, E = Term->getNumOperands(); I != E; ++I) {
|
||||
const MachineOperand &MO = Term->getOperand(I);
|
||||
if (!MO.isReg() || MO.isKill() || MO.isDead()) continue;
|
||||
unsigned Reg = MO.getReg();
|
||||
if (Reg != X86::EFLAGS) continue;
|
||||
|
@ -8513,21 +8522,6 @@ X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
|
|||
sinkMBB->addLiveIn(Reg);
|
||||
}
|
||||
|
||||
// Transfer the remainder of BB and its successor edges to sinkMBB.
|
||||
sinkMBB->splice(sinkMBB->begin(), BB,
|
||||
llvm::next(MachineBasicBlock::iterator(MI)),
|
||||
BB->end());
|
||||
sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
|
||||
|
||||
// Add the true and fallthrough blocks as its successors.
|
||||
BB->addSuccessor(copy0MBB);
|
||||
BB->addSuccessor(sinkMBB);
|
||||
|
||||
// Create the conditional branch instruction.
|
||||
unsigned Opc =
|
||||
X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
|
||||
BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
|
||||
|
||||
// copy0MBB:
|
||||
// %FalseValue = ...
|
||||
// # fallthrough to sinkMBB
|
||||
|
@ -8536,12 +8530,11 @@ X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
|
|||
// sinkMBB:
|
||||
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
|
||||
// ...
|
||||
BuildMI(*sinkMBB, sinkMBB->begin(), DL,
|
||||
TII->get(X86::PHI), MI->getOperand(0).getReg())
|
||||
BuildMI(sinkMBB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg())
|
||||
.addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
|
||||
.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
|
||||
|
||||
MI->eraseFromParent(); // The pseudo instruction is gone now.
|
||||
F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
|
||||
return sinkMBB;
|
||||
}
|
||||
|
||||
|
@ -8550,20 +8543,21 @@ X86TargetLowering::EmitLoweredMingwAlloca(MachineInstr *MI,
|
|||
MachineBasicBlock *BB) const {
|
||||
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
||||
DebugLoc DL = MI->getDebugLoc();
|
||||
MachineFunction *F = BB->getParent();
|
||||
|
||||
// The lowering is pretty easy: we're just emitting the call to _alloca. The
|
||||
// non-trivial part is impdef of ESP.
|
||||
// FIXME: The code should be tweaked as soon as we'll try to do codegen for
|
||||
// mingw-w64.
|
||||
|
||||
BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
|
||||
BuildMI(BB, DL, TII->get(X86::CALLpcrel32))
|
||||
.addExternalSymbol("_alloca")
|
||||
.addReg(X86::EAX, RegState::Implicit)
|
||||
.addReg(X86::ESP, RegState::Implicit)
|
||||
.addReg(X86::EAX, RegState::Define | RegState::Implicit)
|
||||
.addReg(X86::ESP, RegState::Define | RegState::Implicit);
|
||||
|
||||
MI->eraseFromParent(); // The pseudo instruction is gone now.
|
||||
F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
|
||||
return BB;
|
||||
}
|
||||
|
||||
|
@ -8582,38 +8576,35 @@ X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
|
|||
assert(MI->getOperand(3).isGlobal() && "This should be a global");
|
||||
|
||||
if (Subtarget->is64Bit()) {
|
||||
MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
|
||||
TII->get(X86::MOV64rm), X86::RDI)
|
||||
MachineInstrBuilder MIB = BuildMI(BB, DL, TII->get(X86::MOV64rm), X86::RDI)
|
||||
.addReg(X86::RIP)
|
||||
.addImm(0).addReg(0)
|
||||
.addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
|
||||
MI->getOperand(3).getTargetFlags())
|
||||
.addReg(0);
|
||||
MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
|
||||
MIB = BuildMI(BB, DL, TII->get(X86::CALL64m));
|
||||
addDirectMem(MIB, X86::RDI).addReg(0);
|
||||
} else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
|
||||
MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
|
||||
TII->get(X86::MOV32rm), X86::EAX)
|
||||
MachineInstrBuilder MIB = BuildMI(BB, DL, TII->get(X86::MOV32rm), X86::EAX)
|
||||
.addReg(0)
|
||||
.addImm(0).addReg(0)
|
||||
.addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
|
||||
MI->getOperand(3).getTargetFlags())
|
||||
.addReg(0);
|
||||
MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
|
||||
MIB = BuildMI(BB, DL, TII->get(X86::CALL32m));
|
||||
addDirectMem(MIB, X86::EAX).addReg(0);
|
||||
} else {
|
||||
MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
|
||||
TII->get(X86::MOV32rm), X86::EAX)
|
||||
MachineInstrBuilder MIB = BuildMI(BB, DL, TII->get(X86::MOV32rm), X86::EAX)
|
||||
.addReg(TII->getGlobalBaseReg(F))
|
||||
.addImm(0).addReg(0)
|
||||
.addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
|
||||
MI->getOperand(3).getTargetFlags())
|
||||
.addReg(0);
|
||||
MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
|
||||
MIB = BuildMI(BB, DL, TII->get(X86::CALL32m));
|
||||
addDirectMem(MIB, X86::EAX).addReg(0);
|
||||
}
|
||||
|
||||
MI->eraseFromParent(); // The pseudo instruction is gone now.
|
||||
F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
|
||||
return BB;
|
||||
}
|
||||
|
||||
|
@ -8657,25 +8648,23 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|||
// mode when truncating to an integer value.
|
||||
MachineFunction *F = BB->getParent();
|
||||
int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
|
||||
addFrameReference(BuildMI(*BB, MI, DL,
|
||||
TII->get(X86::FNSTCW16m)), CWFrameIdx);
|
||||
addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx);
|
||||
|
||||
// Load the old value of the high byte of the control word...
|
||||
unsigned OldCW =
|
||||
F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
|
||||
addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
|
||||
addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW),
|
||||
CWFrameIdx);
|
||||
|
||||
// Set the high part to be round to zero...
|
||||
addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
|
||||
addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
|
||||
.addImm(0xC7F);
|
||||
|
||||
// Reload the modified control word now...
|
||||
addFrameReference(BuildMI(*BB, MI, DL,
|
||||
TII->get(X86::FLDCW16m)), CWFrameIdx);
|
||||
addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
|
||||
|
||||
// Restore the memory image of control word to original value
|
||||
addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
|
||||
addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
|
||||
.addReg(OldCW);
|
||||
|
||||
// Get the X86 opcode to use.
|
||||
|
@ -8714,14 +8703,13 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|||
} else {
|
||||
AM.Disp = Op.getImm();
|
||||
}
|
||||
addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
|
||||
addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM)
|
||||
.addReg(MI->getOperand(X86AddrNumOperands).getReg());
|
||||
|
||||
// Reload the original control word now.
|
||||
addFrameReference(BuildMI(*BB, MI, DL,
|
||||
TII->get(X86::FLDCW16m)), CWFrameIdx);
|
||||
addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
|
||||
|
||||
MI->eraseFromParent(); // The pseudo instruction is gone now.
|
||||
F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
|
||||
return BB;
|
||||
}
|
||||
// String/text processing lowering.
|
||||
|
|
|
@ -173,14 +173,14 @@ bool X86TargetMachine::addInstSelector(PassManagerBase &PM,
|
|||
// Install an instruction selector.
|
||||
PM.add(createX86ISelDag(*this, OptLevel));
|
||||
|
||||
// Install a pass to insert x87 FP_REG_KILL instructions, as needed.
|
||||
PM.add(createX87FPRegKillInserterPass());
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM,
|
||||
CodeGenOpt::Level OptLevel) {
|
||||
// Install a pass to insert x87 FP_REG_KILL instructions, as needed.
|
||||
PM.add(createX87FPRegKillInserterPass());
|
||||
|
||||
PM.add(createX86MaxStackAlignmentHeuristicPass());
|
||||
return false; // -print-machineinstr shouldn't print after this.
|
||||
}
|
||||
|
|
|
@ -1221,22 +1221,23 @@ XCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|||
MachineFunction *F = BB->getParent();
|
||||
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
|
||||
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
||||
BuildMI(BB, dl, TII.get(XCore::BRFT_lru6))
|
||||
.addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
|
||||
F->insert(It, copy0MBB);
|
||||
F->insert(It, sinkMBB);
|
||||
|
||||
// Transfer the remainder of BB and its successor edges to sinkMBB.
|
||||
sinkMBB->splice(sinkMBB->begin(), BB,
|
||||
llvm::next(MachineBasicBlock::iterator(MI)),
|
||||
BB->end());
|
||||
sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
|
||||
|
||||
// Update machine-CFG edges by first adding all successors of the current
|
||||
// block to the new block which will contain the Phi node for the select.
|
||||
for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
|
||||
E = BB->succ_end(); I != E; ++I)
|
||||
sinkMBB->addSuccessor(*I);
|
||||
// Next, remove all successors of the current block, and add the true
|
||||
// and fallthrough blocks as its successors.
|
||||
while (!BB->succ_empty())
|
||||
BB->removeSuccessor(BB->succ_begin());
|
||||
// Next, add the true and fallthrough blocks as its successors.
|
||||
BB->addSuccessor(copy0MBB);
|
||||
BB->addSuccessor(sinkMBB);
|
||||
|
||||
BuildMI(BB, dl, TII.get(XCore::BRFT_lru6))
|
||||
.addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
|
||||
|
||||
// copy0MBB:
|
||||
// %FalseValue = ...
|
||||
// # fallthrough to sinkMBB
|
||||
|
@ -1249,12 +1250,11 @@ XCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|||
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
|
||||
// ...
|
||||
BB = sinkMBB;
|
||||
BuildMI(*BB, BB->begin(), dl,
|
||||
TII.get(XCore::PHI), MI->getOperand(0).getReg())
|
||||
BuildMI(BB, dl, TII.get(XCore::PHI), MI->getOperand(0).getReg())
|
||||
.addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
|
||||
.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
|
||||
|
||||
MI->eraseFromParent(); // The pseudo instruction is gone now.
|
||||
F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
|
||||
return BB;
|
||||
}
|
||||
|
||||
|
|
Loading…
Reference in New Issue