From f4ebec03e01800ada58f02716a2941d0c6712bd4 Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Thu, 21 Oct 2010 03:40:16 +0000 Subject: [PATCH] putback r116983 and fix simple-fp-encoding.ll tests llvm-svn: 116992 --- llvm/lib/Target/ARM/ARMScheduleA8.td | 22 ++++++++++++++++++++++ llvm/lib/Target/ARM/ARMScheduleA9.td | 8 ++++---- llvm/lib/Target/ARM/ARMScheduleV6.td | 12 ++++++++++++ llvm/test/CodeGen/ARM/fmscs.ll | 2 +- llvm/test/CodeGen/ARM/reg_sequence.ll | 3 ++- llvm/test/MC/ARM/simple-fp-encoding.ll | 24 ++++++++++++------------ 6 files changed, 53 insertions(+), 18 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMScheduleA8.td b/llvm/lib/Target/ARM/ARMScheduleA8.td index 7573182434c6..32d9d66837b3 100644 --- a/llvm/lib/Target/ARM/ARMScheduleA8.td +++ b/llvm/lib/Target/ARM/ARMScheduleA8.td @@ -331,6 +331,28 @@ def CortexA8Itineraries : ProcessorItineraries< InstrItinData, InstrStage<29, [A8_NPipe], 0>, InstrStage<29, [A8_NLSPipe]>], [29, 1]>, + + // + // Integer to Single-precision Move + InstrItinData, + InstrStage<1, [A8_NPipe]>], + [2, 1]>, + // + // Integer to Double-precision Move + InstrItinData, + InstrStage<1, [A8_NPipe]>], + [2, 1, 1]>, + // + // Single-precision to Integer Move + InstrItinData, + InstrStage<1, [A8_NPipe]>], + [20, 1]>, + // + // Double-precision to Integer Move + InstrItinData, + InstrStage<1, [A8_NPipe]>], + [20, 20, 1]>, + // // Single-precision FP Load InstrItinData, diff --git a/llvm/lib/Target/ARM/ARMScheduleA9.td b/llvm/lib/Target/ARM/ARMScheduleA9.td index c22367716c30..548bc7cd6030 100644 --- a/llvm/lib/Target/ARM/ARMScheduleA9.td +++ b/llvm/lib/Target/ARM/ARMScheduleA9.td @@ -641,7 +641,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, InstrStage<1, [A9_NPipe]>], - [1, 1]>, + [2, 1]>, // // Double-precision to Integer Move InstrItinData, @@ -649,7 +649,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, InstrStage<1, [A9_NPipe]>], - [1, 1, 1]>, + [2, 1, 1]>, // // Single-precision FP Load InstrItinData, @@ -1430,7 +1430,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, InstrStage<1, [A9_NPipe]>], - [2, 1]>, + [1, 1]>, // // Integer to Double-precision Move InstrItinData, @@ -1438,7 +1438,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, InstrStage<1, [A9_NPipe]>], - [2, 1, 1]>, + [1, 1, 1]>, // // Single-precision to Integer Move InstrItinData, diff --git a/llvm/lib/Target/ARM/ARMScheduleV6.td b/llvm/lib/Target/ARM/ARMScheduleV6.td index b845130e3701..e4e9c13bd935 100644 --- a/llvm/lib/Target/ARM/ARMScheduleV6.td +++ b/llvm/lib/Target/ARM/ARMScheduleV6.td @@ -247,6 +247,18 @@ def ARMV6Itineraries : ProcessorItineraries< // Double-precision FP SQRT InstrItinData], [34, 2, 2]>, // + // Integer to Single-precision Move + InstrItinData], [10, 1]>, + // + // Integer to Double-precision Move + InstrItinData], [10, 1, 1]>, + // + // Single-precision to Integer Move + InstrItinData], [10, 1]>, + // + // Double-precision to Integer Move + InstrItinData], [10, 10, 1]>, + // // Single-precision FP Load InstrItinData], [5, 2, 2]>, // diff --git a/llvm/test/CodeGen/ARM/fmscs.ll b/llvm/test/CodeGen/ARM/fmscs.ll index 103ce334519b..19359a1ae6bc 100644 --- a/llvm/test/CodeGen/ARM/fmscs.ll +++ b/llvm/test/CodeGen/ARM/fmscs.ll @@ -19,6 +19,6 @@ entry: ; NFP0: vnmls.f32 s2, s1, s0 ; CORTEXA8: test: -; CORTEXA8: vnmls.f32 s2, s1, s0 +; CORTEXA8: vnmls.f32 s1, s2, s0 ; CORTEXA9: test: ; CORTEXA9: vnmls.f32 s0, s1, s2 diff --git a/llvm/test/CodeGen/ARM/reg_sequence.ll b/llvm/test/CodeGen/ARM/reg_sequence.ll index 1a95897c26cf..390955472ec0 100644 --- a/llvm/test/CodeGen/ARM/reg_sequence.ll +++ b/llvm/test/CodeGen/ARM/reg_sequence.ll @@ -75,7 +75,8 @@ define <8 x i8> @t3(i8* %A, i8* %B) nounwind { ; CHECK: t3: ; CHECK: vld3.8 ; CHECK: vmul.i8 -; CHECK-NOT: vmov +; CHECK: vmov r +; CHECK-NOT: vmov d ; CHECK: vst3.8 %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2] %tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0 ; <<8 x i8>> [#uses=1] diff --git a/llvm/test/MC/ARM/simple-fp-encoding.ll b/llvm/test/MC/ARM/simple-fp-encoding.ll index 230fc87df751..3e05b0ab688d 100644 --- a/llvm/test/MC/ARM/simple-fp-encoding.ll +++ b/llvm/test/MC/ARM/simple-fp-encoding.ll @@ -269,7 +269,7 @@ entry: define float @f91(float %a, float %b, float %c) nounwind readnone { entry: ; CHECK: f91 -; CHECK: vmla.f32 s2, s1, s0 @ encoding: [0x80,0x1a,0x00,0xee] +; CHECK: vmla.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x41,0xee] %mul = fmul float %a, %b %add = fadd float %mul, %c ret float %add @@ -287,7 +287,7 @@ entry: define float @f93(float %a, float %b, float %c) nounwind readnone { entry: ; CHECK: f93 -; CHECK: vmls.f32 s2, s1, s0 @ encoding: [0xc0,0x1a,0x00,0xee] +; CHECK: vmls.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x41,0xee] %mul = fmul float %a, %b %sub = fsub float %c, %mul ret float %sub @@ -306,7 +306,7 @@ entry: define float @f95(float %a, float %b, float %c) nounwind readnone { entry: ; CHECK: f95 -; CHECK: vnmla.f32 s2, s1, s0 @ encoding: [0xc0,0x1a,0x10,0xee] +; CHECK: vnmla.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x51,0xee] %mul = fmul float %a, %b %sub = fsub float -0.000000e+00, %mul %sub3 = fsub float %sub, %c @@ -325,7 +325,7 @@ entry: define float @f97(float %a, float %b, float %c) nounwind readnone { entry: ; CHECK: f97 -; CHECK: vnmls.f32 s2, s1, s0 @ encoding: [0x80,0x1a,0x10,0xee] +; CHECK: vnmls.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x51,0xee] %mul = fmul float %a, %b %sub = fsub float %mul, %c ret float %sub @@ -404,10 +404,10 @@ entry: define void @f104(float %a, float %b, float %c, float %d, float %e, float %f) nounwind { entry: ; CHECK: f104 -; CHECK: vmov s2, r0 @ encoding: [0x10,0x0a,0x01,0xee] -; CHECK: vmov s3, r1 @ encoding: [0x90,0x1a,0x01,0xee] -; CHECK: vmov s4, r2 @ encoding: [0x10,0x2a,0x02,0xee] -; CHECK: vmov s5, r3 @ encoding: [0x90,0x3a,0x02,0xee] +; CHECK: vmov s0, r0 @ encoding: [0x10,0x0a,0x00,0xee] +; CHECK: vmov s1, r1 @ encoding: [0x90,0x1a,0x00,0xee] +; CHECK: vmov s2, r2 @ encoding: [0x10,0x2a,0x01,0xee] +; CHECK: vmov s3, r3 @ encoding: [0x90,0x3a,0x01,0xee] %conv = fptosi float %a to i32 %conv2 = fptosi float %b to i32 %conv4 = fptosi float %c to i32 @@ -415,10 +415,10 @@ entry: %conv8 = fptosi float %e to i32 %conv10 = fptosi float %f to i32 tail call void @g104(i32 %conv, i32 %conv2, i32 %conv4, i32 %conv6, i32 %conv8, i32 %conv10) nounwind -; CHECK: vmov r0, s2 @ encoding: [0x10,0x0a,0x11,0xee] -; CHECK: vmov r1, s3 @ encoding: [0x90,0x1a,0x11,0xee] -; CHECK: vmov r2, s4 @ encoding: [0x10,0x2a,0x12,0xee] -; CHECK: vmov r3, s5 @ encoding: [0x90,0x3a,0x12,0xee] +; CHECK: vmov r0, s0 @ encoding: [0x10,0x0a,0x10,0xee] +; CHECK: vmov r1, s1 @ encoding: [0x90,0x1a,0x10,0xee] +; CHECK: vmov r2, s2 @ encoding: [0x10,0x2a,0x11,0xee] +; CHECK: vmov r3, s3 @ encoding: [0x90,0x3a,0x11,0xee] ret void }