forked from OSchip/llvm-project
Chris Lattner
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//===-- llvm/CodeGen/MBasicBlock.h - Machine Specific BB rep ----*- C++ -*-===//
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//
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// This class provides a way to represent a basic block in a machine-specific
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// form. A basic block is represented as a list of machine specific
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// instructions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef CODEGEN_MBASICBLOCK_H
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#define CODEGEN_MBASICBLOCK_H
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#include "llvm/CodeGen/MInstruction.h"
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#include "Support/ilist"
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class MBasicBlock {
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MBasicBlock *Prev, *Next;
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iplist<MInstruction> InstList;
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// FIXME: we should maintain a pointer to the function we are embedded into!
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public:
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MBasicBlock() {}
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// Provide accessors for the MBasicBlock list...
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typedef iplist<MInstruction> InstListType;
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typedef InstListType::iterator iterator;
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typedef InstListType::const_iterator const_iterator;
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typedef std::reverse_iterator<const_iterator> const_reverse_iterator;
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typedef std::reverse_iterator<iterator> reverse_iterator;
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//===--------------------------------------------------------------------===//
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/// Instruction iterator methods
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///
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inline iterator begin() { return InstList.begin(); }
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inline const_iterator begin() const { return InstList.begin(); }
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inline iterator end () { return InstList.end(); }
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inline const_iterator end () const { return InstList.end(); }
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inline reverse_iterator rbegin() { return InstList.rbegin(); }
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inline const_reverse_iterator rbegin() const { return InstList.rbegin(); }
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inline reverse_iterator rend () { return InstList.rend(); }
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inline const_reverse_iterator rend () const { return InstList.rend(); }
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inline unsigned size() const { return InstList.size(); }
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inline bool empty() const { return InstList.empty(); }
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inline const MInstruction &front() const { return InstList.front(); }
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inline MInstruction &front() { return InstList.front(); }
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inline const MInstruction &back() const { return InstList.back(); }
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inline MInstruction &back() { return InstList.back(); }
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/// getInstList() - Return the underlying instruction list container. You
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/// need to access it directly if you want to modify it currently.
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///
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const InstListType &getInstList() const { return InstList; }
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InstListType &getInstList() { return InstList; }
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private: // Methods used to maintain doubly linked list of blocks...
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friend class ilist_traits<MBasicBlock>;
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MBasicBlock *getPrev() const { return Prev; }
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MBasicBlock *getNext() const { return Next; }
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void setPrev(MBasicBlock *P) { Prev = P; }
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void setNext(MBasicBlock *N) { Next = N; }
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};
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#endif
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//===-- llvm/CodeGen/MInstruction.h - Machine Instruction -------*- C++ -*-===//
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//
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// This class represents a single machine instruction for the LLVM backend.
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// This instruction is represented in a completely generic way to allow all
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// backends to share a common representation. MInstructions are embedded into
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// MBasicBlocks, and are maintained as a doubly linked list.
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//
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// Because there are a lot of machine instruction that may be in use at a time
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// (being manipulated), we are sure to keep a very compact representation that
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// is extremely light-weight.
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//
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// This class is used to represent an instruction when it is in SSA form as well
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// as when it has been register allocated to use physical registers.
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//
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// FIXME: This should eventually be merged with the MachineInstr class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef CODEGEN_MINSTRUCTION_H
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#define CODEGEN_MINSTRUCTION_H
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#include <vector>
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template<typename NodeTy> struct ilist_traits;
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class MBasicBlock;
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/// MOperand - This class represents a single operand in an instruction.
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/// Interpretation of this operand is not really possible without information
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/// from the machine instruction that it is embedded into.
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///
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class MOperand {
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union {
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unsigned uVal;
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int iVal;
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};
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public:
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MOperand(unsigned Value) : uVal(Value) {}
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MOperand(int Value) : iVal(Value) {}
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/// Interpretation - This enum is used by the MInstruction class to interpret
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/// the untyped value field of the operand.
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enum Interpretation {
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Register, // This is some register number
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SignExtImmediate, // This is a sign extended immediate
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ZeroExtImmediate, // This is a zero extended immediate
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PCRelativeDisp // This is a displacement relative to the PC
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// FIXME: We need a symbolic value here, like global variable address
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};
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unsigned getUnsignedValue() const { return uVal; }
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unsigned getSignedValue() const { return iVal; }
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};
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/// MInstruction - Represent a single machine instruction in the code generator.
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/// This is meant to be a light weight representation that is completely
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/// independant of the target machine being code generated for.
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///
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class MInstruction {
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MInstruction *Prev, *Next; // Doubly linked list of instructions...
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unsigned Opcode; // Opcode of the instruction
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unsigned Dest; // Destination register written (or 0 if none)
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std::vector<MOperand> Operands; // Operands of the instruction...
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/// OperandInterpretation - This array specifies how the operands of the
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/// instruction are to be interpreted (is it a register?, an immediate
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/// constant?, a PC relative displacement?, etc...). Only four values are
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/// allowed, so any instruction with more than four operands (should be
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/// exceedingly rare, perhaps only PHI nodes) are assumed to have register
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/// operands beyond the fourth.
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///
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unsigned char OperandInterpretation[4];
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public:
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/// MInstruction ctor - Create a new machine instruction, with the specified
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/// opcode and destination register. Operands are then added with the
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/// addOperand method.
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///
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MInstruction(unsigned O = 0, unsigned D = 0) : Opcode(O), Dest(D) {}
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/// MInstruction ctor - Create a new instruction, and append it to the
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/// specified basic block.
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///
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MInstruction(MBasicBlock *BB, unsigned Opcode = 0, unsigned Dest = 0);
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/// getOpcode - Return the opcode for this machine instruction. The value of
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/// the opcode defines how to interpret the operands of the instruction.
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///
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unsigned getOpcode() const { return Opcode; }
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/// getDestinationReg - This method returns the register written to by this
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/// instruction. If this returns zero, the instruction does not produce a
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/// value, because register #0 is always the garbage marker.
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///
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unsigned getDestinationReg() const { return Dest; }
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/// setDestinationReg - This method changes the register written to by this
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/// instruction. Note that if SSA form is currently active then the SSA table
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/// needs to be updated to match this, thus this method shouldn't be used
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/// directly.
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///
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void setDestinationReg(unsigned R) { Dest = R; }
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/// getNumOperands - Return the number of operands the instruction currently
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/// has.
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///
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unsigned getNumOperands() const { return Operands.size(); }
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/// getOperandInterpretation - Return the interpretation of operand #Op
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///
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MOperand::Interpretation getOperandInterpretation(unsigned Op) const {
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if (Op < 4) return (MOperand::Interpretation)OperandInterpretation[Op];
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return MOperand::Register; // Operands >= 4 are all registers
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}
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unsigned getRegisterOperand(unsigned Op) const {
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assert(getOperandInterpretation(Op) == MOperand::Register &&
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"Operand isn't a register!");
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return Operands[Op].getUnsignedValue();
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}
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int getSignExtOperand(unsigned Op) const {
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assert(getOperandInterpretation(Op) == MOperand::SignExtImmediate &&
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"Operand isn't a sign extended immediate!");
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return Operands[Op].getSignedValue();
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}
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unsigned getZeroExtOperand(unsigned Op) const {
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assert(getOperandInterpretation(Op) == MOperand::ZeroExtImmediate &&
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"Operand isn't a zero extended immediate!");
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return Operands[Op].getUnsignedValue();
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}
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int getPCRelativeOperand(unsigned Op) const {
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assert(getOperandInterpretation(Op) == MOperand::PCRelativeDisp &&
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"Operand isn't a PC relative displacement!");
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return Operands[Op].getSignedValue();
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}
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/// addOperand - Add a new operand to the instruction with the specified value
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/// and interpretation.
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///
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void addOperand(unsigned Value, MOperand::Interpretation Ty);
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private: // Methods used to maintain doubly linked list of instructions...
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friend class ilist_traits<MInstruction>;
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MInstruction *getPrev() const { return Prev; }
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MInstruction *getNext() const { return Next; }
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void setPrev(MInstruction *P) { Prev = P; }
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void setNext(MInstruction *N) { Next = N; }
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};
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#endif
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@ -1,31 +0,0 @@
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//===-- MInstruction.cpp - Implementation code for the MInstruction class -===//
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//
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// This file contains a printer that converts from our internal representation
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// of LLVM code to a nice human readable form that is suitable for debuggging.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MBasicBlock.h"
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/// MInstruction ctor - Create a new instruction, and append it to the
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/// specified basic block.
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///
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MInstruction::MInstruction(MBasicBlock *BB, unsigned O, unsigned D)
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: Opcode(O), Dest(D) {
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// Add this instruction to the specified basic block
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BB->getInstList().push_back(this);
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}
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/// addOperand - Add a new operand to the instruction with the specified value
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/// and interpretation.
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///
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void MInstruction::addOperand(unsigned Value, MOperand::Interpretation Ty) {
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if (Operands.size() < 4) {
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OperandInterpretation[Operands.size()] = Ty; // Save interpretation
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} else {
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assert(Ty == MOperand::Register &&
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"Trying to add 5th operand that is not a register to MInstruction!");
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}
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Operands.push_back(Value);
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}
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