forked from OSchip/llvm-project
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6a8e5f4b0f
commit
f4dcc42e7b
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@ -2216,7 +2216,6 @@ const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case HexagonISD::INSERT: return "HexagonISD::INSERT";
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case HexagonISD::INSERTRP: return "HexagonISD::INSERTRP";
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case HexagonISD::JT: return "HexagonISD::JT";
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case HexagonISD::PACKHL: return "HexagonISD::PACKHL";
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case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG";
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case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
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case HexagonISD::VCOMBINE: return "HexagonISD::VCOMBINE";
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@ -51,7 +51,6 @@ namespace HexagonISD {
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CP, // Constant pool.
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COMBINE,
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PACKHL,
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VSPLAT,
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VASL,
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VASR,
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@ -464,7 +464,7 @@ def: Pat<(v4i8 (trunc V4I16:$Rs)),
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// S2_vtruneh
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def: Pat<(v2i16 (trunc V2I32:$Rs)),
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(LoReg (S2_packhl (HiReg $Rs), (LoReg $Rs)))>;
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(A2_combine_ll (HiReg $Rs), (LoReg $Rs))>;
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// --(4) Logical ---------------------------------------------------------
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@ -946,14 +946,11 @@ def SDTHexagonVCOMBINE: SDTypeProfile<1, 2, [SDTCisSameAs<1, 2>,
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SDTCisSubVecOfVec<1, 0>]>;
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def SDTHexagonVPACK: SDTypeProfile<1, 2, [SDTCisSameAs<1, 2>, SDTCisVec<1>]>;
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def HexagonPACKHL: SDNode<"HexagonISD::PACKHL", SDTHexagonI64I32I32>;
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def HexagonCOMBINE: SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>;
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def HexagonVCOMBINE: SDNode<"HexagonISD::VCOMBINE", SDTHexagonVCOMBINE>;
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def HexagonVPACKE: SDNode<"HexagonISD::VPACKE", SDTHexagonVPACK>;
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def HexagonVPACKO: SDNode<"HexagonISD::VPACKO", SDTHexagonVPACK>;
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def: OpR_RR_pat<S2_packhl, pf2<HexagonPACKHL>, i64, I32>;
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def: Pat<(HexagonCOMBINE I32:$Rs, I32:$Rt), (Combinew $Rs, $Rt)>;
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// The complexity of the combines involving immediates should be greater
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@ -1,6 +1,6 @@
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; Extracted from test/CodeGen/Generic/vector-casts.ll: used to loop indefinitely.
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK: packhl
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; CHECK: combine
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define void @a(<2 x double>* %p, <2 x i8>* %q) {
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%t = load <2 x double>, <2 x double>* %p
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