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AMDGPU/GlobalISel: Fix bit ops for non-power-of-2 sizes 

llvm-svn: 354825
This commit is contained in:
Matt Arsenault 2019-02-25 21:32:48 +00:00
parent 0a3fe502e6
commit f4bfe4cd17
10 changed files with 120 additions and 28 deletions
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2
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
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@ -174,6 +174,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
.clampScalar(0, S32, S64)
.moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
.fewerElementsIf(vectorWiderThan(0, 32), fewerEltsToSize64Vector(0))
.widenScalarToNextPow2(0)
.scalarize(0);
getActionDefinitionsBuilder({G_UADDO, G_SADDO, G_USUBO, G_SSUBO,
@ -270,6 +271,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
.legalFor({{S64, S32}, {S32, S16}, {S64, S16},
{S32, S1}, {S64, S1}, {S16, S1},
// FIXME: Hack
{S64, LLT::scalar(33)},
{S32, S8}, {S128, S32}, {S128, S64}, {S32, LLT::scalar(24)}})
.scalarize(0);

23
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
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@ -147,6 +147,29 @@ body: |
$vgpr0 = COPY %5
...
---
name: test_and_s48
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: test_and_s48
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND]](s64)
; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s48) = G_TRUNC %0
%3:_(s48) = G_TRUNC %1
%4:_(s48) = G_AND %2, %3
%5:_(s64) = G_ANYEXT %4
$vgpr0_vgpr1 = COPY %5
...
---
name: test_and_v2s32
body: |

6
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir
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@ -205,8 +205,10 @@ body: |
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C2]]
; CHECK: $vgpr0_vgpr1 = COPY [[AND1]](s64)
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C2]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s33) = G_TRUNC %0
%2:_(s33) = G_CTLZ_ZERO_UNDEF %1

6
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
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@ -205,8 +205,10 @@ body: |
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C2]]
; CHECK: $vgpr0_vgpr1 = COPY [[AND1]](s64)
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C2]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s33) = G_TRUNC %0
%2:_(s33) = G_CTLZ %1

6
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
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@ -191,8 +191,10 @@ body: |
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTPOP]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[ZEXT]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C1]]
; CHECK: $vgpr0_vgpr1 = COPY [[AND1]](s64)
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C1]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s33) = G_TRUNC %0
%2:_(s33) = G_CTPOP %1

6
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir
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@ -191,8 +191,10 @@ body: |
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTTZ_ZERO_UNDEF]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[ZEXT]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C1]]
; CHECK: $vgpr0_vgpr1 = COPY [[AND1]](s64)
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C1]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s33) = G_TRUNC %0
%2:_(s33) = G_CTTZ_ZERO_UNDEF %1

6
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
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@ -201,8 +201,10 @@ body: |
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTTZ]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[ZEXT]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C2]]
; CHECK: $vgpr0_vgpr1 = COPY [[AND1]](s64)
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C2]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s33) = G_TRUNC %0
%2:_(s33) = G_CTTZ %1

23
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
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@ -147,6 +147,29 @@ body: |
$vgpr0 = COPY %5
...
---
name: test_or_s48
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: test_or_s48
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY2]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[OR]](s64)
; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s48) = G_TRUNC %0
%3:_(s48) = G_TRUNC %1
%4:_(s48) = G_OR %2, %3
%5:_(s64) = G_ANYEXT %4
$vgpr0_vgpr1 = COPY %5
...
---
name: test_or_v2s32
body: |

47
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
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@ -199,24 +199,35 @@ body: |
liveins: $vgpr0
; CHECK-LABEL: name: test_unmerge_s1_s3
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:_(s3) = G_TRUNC [[COPY]](s32)
; CHECK: [[ZEXT:%[0-9]+]]:_(s48) = G_ZEXT [[TRUNC]](s3)
; CHECK: [[C:%[0-9]+]]:_(s48) = G_CONSTANT i48 15
; CHECK: [[SHL:%[0-9]+]]:_(s48) = G_SHL [[ZEXT]], [[C]](s48)
; CHECK: [[OR:%[0-9]+]]:_(s48) = G_OR [[ZEXT]], [[SHL]]
; CHECK: [[C1:%[0-9]+]]:_(s48) = G_CONSTANT i48 30
; CHECK: [[SHL1:%[0-9]+]]:_(s48) = G_SHL [[OR]], [[C1]](s48)
; CHECK: [[OR1:%[0-9]+]]:_(s48) = G_OR [[OR]], [[SHL1]]
; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[OR1]](s48)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[UV]](s16)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s1)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[UV1]](s16)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC2]](s1)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s1) = G_TRUNC [[UV2]](s16)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC3]](s1)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
; CHECK: $vgpr1 = COPY [[ANYEXT1]](s32)
; CHECK: $vgpr2 = COPY [[ANYEXT2]](s32)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
; CHECK: [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[C]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[TRUNC]](s48)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND]], [[TRUNC1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT1]], [[C2]]
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[SHL]](s64)
; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[COPY1]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s48) = G_TRUNC [[OR]](s64)
; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 30
; CHECK: [[TRUNC3:%[0-9]+]]:_(s48) = G_TRUNC [[C3]](s64)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[TRUNC3]](s48)
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[OR]](s64)
; CHECK: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY2]], [[TRUNC4]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[OR]](s64)
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[SHL1]](s64)
; CHECK: [[OR1:%[0-9]+]]:_(s64) = G_OR [[COPY3]], [[COPY4]]
; CHECK: [[TRUNC5:%[0-9]+]]:_(s48) = G_TRUNC [[OR1]](s64)
; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[TRUNC5]](s48)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s16)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)
; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT2]](s32)
; CHECK: $vgpr1 = COPY [[ANYEXT3]](s32)
; CHECK: $vgpr2 = COPY [[ANYEXT4]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s3) = G_TRUNC %0
%2:_(s1), %3:_(s1), %4:_(s1) = G_UNMERGE_VALUES %1

23
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
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@ -147,6 +147,29 @@ body: |
$vgpr0 = COPY %5
...
---
name: test_xor_s48
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: test_xor_s48
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY2]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[XOR]](s64)
; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s48) = G_TRUNC %0
%3:_(s48) = G_TRUNC %1
%4:_(s48) = G_XOR %2, %3
%5:_(s64) = G_ANYEXT %4
$vgpr0_vgpr1 = COPY %5
...
---
name: test_xor_v2s32
body: |