forked from OSchip/llvm-project
[InstCombine] Add baseline tests for redundant sign bits count folds
Add baseline tests. NFC. (https://github.com/llvm/llvm-project/issues/56479) Test plan: ninja check-all Differential revision: https://reviews.llvm.org/D130605
This commit is contained in:
Alexander Shaposhnikov
parent
c4c68b676e
commit
f4aa08586a
|
|
@ -4111,6 +4111,211 @@ define i1 @signbit_true_logic_uses_commute(i64 %x) {
|
|||
ret i1 %r
|
||||
}
|
||||
|
||||
define i1 @redundant_sign_bit_count_ult_1_2(i32 %x) {
|
||||
; CHECK-LABEL: @redundant_sign_bit_count_ult_1_2(
|
||||
; CHECK-NEXT: [[Y:%.*]] = ashr i32 [[X:%.*]], 1
|
||||
; CHECK-NEXT: [[Z:%.*]] = xor i32 [[Y]], [[X]]
|
||||
; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[Z]], 4
|
||||
; CHECK-NEXT: ret i1 [[C]]
|
||||
;
|
||||
%y = ashr i32 %x, 1
|
||||
%z = xor i32 %y, %x
|
||||
%c = icmp ult i32 %z, 4
|
||||
ret i1 %c
|
||||
}
|
||||
|
||||
define i1 @redundant_sign_bit_count_ult_1_30(i32 %x) {
|
||||
; CHECK-LABEL: @redundant_sign_bit_count_ult_1_30(
|
||||
; CHECK-NEXT: [[Y:%.*]] = ashr i32 [[X:%.*]], 1
|
||||
; CHECK-NEXT: [[Z:%.*]] = xor i32 [[Y]], [[X]]
|
||||
; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[Z]], 1073741824
|
||||
; CHECK-NEXT: ret i1 [[C]]
|
||||
;
|
||||
%y = ashr i32 %x, 1
|
||||
%z = xor i32 %y, %x
|
||||
%c = icmp ult i32 %z, 1073741824
|
||||
ret i1 %c
|
||||
}
|
||||
|
||||
define i1 @redundant_sign_bit_count_ult_31_2(i32 %x) {
|
||||
; CHECK-LABEL: @redundant_sign_bit_count_ult_31_2(
|
||||
; CHECK-NEXT: [[Y:%.*]] = ashr i32 [[X:%.*]], 31
|
||||
; CHECK-NEXT: [[Z:%.*]] = xor i32 [[Y]], [[X]]
|
||||
; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[Z]], 4
|
||||
; CHECK-NEXT: ret i1 [[C]]
|
||||
;
|
||||
%y = ashr i32 %x, 31
|
||||
%z = xor i32 %y, %x
|
||||
%c = icmp ult i32 %z, 4
|
||||
ret i1 %c
|
||||
}
|
||||
|
||||
define i1 @redundant_sign_bit_count_ult_31_30(i32 %x) {
|
||||
; CHECK-LABEL: @redundant_sign_bit_count_ult_31_30(
|
||||
; CHECK-NEXT: [[Y:%.*]] = ashr i32 [[X:%.*]], 31
|
||||
; CHECK-NEXT: [[Z:%.*]] = xor i32 [[Y]], [[X]]
|
||||
; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[Z]], 1073741824
|
||||
; CHECK-NEXT: ret i1 [[C]]
|
||||
;
|
||||
%y = ashr i32 %x, 31
|
||||
%z = xor i32 %y, %x
|
||||
%c = icmp ult i32 %z, 1073741824
|
||||
ret i1 %c
|
||||
}
|
||||
|
||||
declare void @use_i32(i32)
|
||||
|
||||
define i1 @redundant_sign_bit_count_ult_31_30_extra_use_ashr(i32 %x) {
|
||||
; CHECK-LABEL: @redundant_sign_bit_count_ult_31_30_extra_use_ashr(
|
||||
; CHECK-NEXT: [[Y:%.*]] = ashr i32 [[X:%.*]], 31
|
||||
; CHECK-NEXT: call void @use_i32(i32 [[Y]])
|
||||
; CHECK-NEXT: [[Z:%.*]] = xor i32 [[Y]], [[X]]
|
||||
; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[Z]], 1073741824
|
||||
; CHECK-NEXT: ret i1 [[C]]
|
||||
;
|
||||
%y = ashr i32 %x, 31
|
||||
call void @use_i32(i32 %y)
|
||||
%z = xor i32 %y, %x
|
||||
%c = icmp ult i32 %z, 1073741824
|
||||
ret i1 %c
|
||||
}
|
||||
|
||||
define i1 @redundant_sign_bit_count_ult_31_30_extra_use_xor(i32 %x) {
|
||||
; CHECK-LABEL: @redundant_sign_bit_count_ult_31_30_extra_use_xor(
|
||||
; CHECK-NEXT: [[Y:%.*]] = ashr i32 [[X:%.*]], 31
|
||||
; CHECK-NEXT: [[Z:%.*]] = xor i32 [[Y]], [[X]]
|
||||
; CHECK-NEXT: call void @use_i32(i32 [[Z]])
|
||||
; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[Z]], 1073741824
|
||||
; CHECK-NEXT: ret i1 [[C]]
|
||||
;
|
||||
%y = ashr i32 %x, 31
|
||||
%z = xor i32 %y, %x
|
||||
call void @use_i32(i32 %z)
|
||||
%c = icmp ult i32 %z, 1073741824
|
||||
ret i1 %c
|
||||
}
|
||||
|
||||
define i1 @not_redundant_sign_bit_count_ult(i32 %w, i32 %x) {
|
||||
; CHECK-LABEL: @not_redundant_sign_bit_count_ult(
|
||||
; CHECK-NEXT: [[Y:%.*]] = ashr i32 [[X:%.*]], 31
|
||||
; CHECK-NEXT: [[Z:%.*]] = xor i32 [[Y]], [[W:%.*]]
|
||||
; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[Z]], 1073741824
|
||||
; CHECK-NEXT: ret i1 [[C]]
|
||||
;
|
||||
%y = ashr i32 %x, 31
|
||||
%z = xor i32 %y, %w
|
||||
%c = icmp ult i32 %z, 1073741824
|
||||
ret i1 %c
|
||||
}
|
||||
|
||||
define i1 @wrong_shift_opcode_i8(i8 %x) {
|
||||
; CHECK-LABEL: @wrong_shift_opcode_i8(
|
||||
; CHECK-NEXT: [[Y:%.*]] = lshr i8 [[X:%.*]], 5
|
||||
; CHECK-NEXT: [[Z:%.*]] = xor i8 [[Y]], [[X]]
|
||||
; CHECK-NEXT: [[C:%.*]] = icmp ult i8 [[Z]], 2
|
||||
; CHECK-NEXT: ret i1 [[C]]
|
||||
;
|
||||
%y = lshr i8 %x, 5
|
||||
%z = xor i8 %y, %x
|
||||
%c = icmp ult i8 %z, 2
|
||||
ret i1 %c
|
||||
}
|
||||
|
||||
define i1 @redundant_sign_bit_count_ult_31_30_commute(i32 %xsrc) {
|
||||
; CHECK-LABEL: @redundant_sign_bit_count_ult_31_30_commute(
|
||||
; CHECK-NEXT: [[X:%.*]] = mul i32 [[XSRC:%.*]], 13
|
||||
; CHECK-NEXT: [[Y:%.*]] = ashr i32 [[X]], 31
|
||||
; CHECK-NEXT: [[Z:%.*]] = xor i32 [[X]], [[Y]]
|
||||
; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[Z]], 1073741824
|
||||
; CHECK-NEXT: ret i1 [[C]]
|
||||
;
|
||||
%x = mul i32 %xsrc, 13 ; thwart complexity-based canonicalization
|
||||
%y = ashr i32 %x, 31
|
||||
%z = xor i32 %x, %y
|
||||
%c = icmp ult i32 %z, 1073741824
|
||||
ret i1 %c
|
||||
}
|
||||
|
||||
define i1 @redundant_sign_bit_count_i8(i8 %x) {
|
||||
; CHECK-LABEL: @redundant_sign_bit_count_i8(
|
||||
; CHECK-NEXT: [[Y:%.*]] = ashr i8 [[X:%.*]], 5
|
||||
; CHECK-NEXT: [[Z:%.*]] = xor i8 [[Y]], [[X]]
|
||||
; CHECK-NEXT: [[C:%.*]] = icmp ult i8 [[Z]], 2
|
||||
; CHECK-NEXT: ret i1 [[C]]
|
||||
;
|
||||
%y = ashr i8 %x, 5
|
||||
%z = xor i8 %y, %x
|
||||
%c = icmp ult i8 %z, 2
|
||||
ret i1 %c
|
||||
}
|
||||
|
||||
define <2 x i1> @redundant_sign_bit_count_ult_31_30_vector(<2 x i32> %xsrc) {
|
||||
; CHECK-LABEL: @redundant_sign_bit_count_ult_31_30_vector(
|
||||
; CHECK-NEXT: [[X:%.*]] = mul <2 x i32> [[XSRC:%.*]], <i32 13, i32 13>
|
||||
; CHECK-NEXT: [[Y:%.*]] = ashr <2 x i32> [[X]], <i32 31, i32 31>
|
||||
; CHECK-NEXT: [[Z:%.*]] = xor <2 x i32> [[X]], [[Y]]
|
||||
; CHECK-NEXT: [[C:%.*]] = icmp ult <2 x i32> [[Z]], <i32 1073741824, i32 1073741824>
|
||||
; CHECK-NEXT: ret <2 x i1> [[C]]
|
||||
;
|
||||
%x = mul <2 x i32> %xsrc, <i32 13, i32 13> ; thwart complexity-based canonicalization
|
||||
%y = ashr <2 x i32> %x, <i32 31, i32 31>
|
||||
%z = xor <2 x i32> %x, %y
|
||||
%c = icmp ult <2 x i32> %z, <i32 1073741824, i32 1073741824>
|
||||
ret <2 x i1> %c
|
||||
}
|
||||
|
||||
define i1 @redundant_sign_bit_count_ugt_1_2(i32 %x) {
|
||||
; CHECK-LABEL: @redundant_sign_bit_count_ugt_1_2(
|
||||
; CHECK-NEXT: [[Y:%.*]] = ashr i32 [[X:%.*]], 1
|
||||
; CHECK-NEXT: [[Z:%.*]] = xor i32 [[Y]], [[X]]
|
||||
; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[Z]], 3
|
||||
; CHECK-NEXT: ret i1 [[C]]
|
||||
;
|
||||
%y = ashr i32 %x, 1
|
||||
%z = xor i32 %y, %x
|
||||
%c = icmp ugt i32 %z, 3
|
||||
ret i1 %c
|
||||
}
|
||||
|
||||
define i1 @redundant_sign_bit_count_ugt_1_30(i32 %x) {
|
||||
; CHECK-LABEL: @redundant_sign_bit_count_ugt_1_30(
|
||||
; CHECK-NEXT: [[Y:%.*]] = ashr i32 [[X:%.*]], 1
|
||||
; CHECK-NEXT: [[Z:%.*]] = xor i32 [[Y]], [[X]]
|
||||
; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[Z]], 1073741823
|
||||
; CHECK-NEXT: ret i1 [[C]]
|
||||
;
|
||||
%y = ashr i32 %x, 1
|
||||
%z = xor i32 %y, %x
|
||||
%c = icmp ugt i32 %z, 1073741823
|
||||
ret i1 %c
|
||||
}
|
||||
|
||||
define i1 @redundant_sign_bit_count_ugt_31_2(i32 %x) {
|
||||
; CHECK-LABEL: @redundant_sign_bit_count_ugt_31_2(
|
||||
; CHECK-NEXT: [[Y:%.*]] = ashr i32 [[X:%.*]], 31
|
||||
; CHECK-NEXT: [[Z:%.*]] = xor i32 [[Y]], [[X]]
|
||||
; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[Z]], 3
|
||||
; CHECK-NEXT: ret i1 [[C]]
|
||||
;
|
||||
%y = ashr i32 %x, 31
|
||||
%z = xor i32 %y, %x
|
||||
%c = icmp ugt i32 %z, 3
|
||||
ret i1 %c
|
||||
}
|
||||
|
||||
define i1 @redundant_sign_bit_count_ugt_31_30(i32 %x) {
|
||||
; CHECK-LABEL: @redundant_sign_bit_count_ugt_31_30(
|
||||
; CHECK-NEXT: [[Y:%.*]] = ashr i32 [[X:%.*]], 31
|
||||
; CHECK-NEXT: [[Z:%.*]] = xor i32 [[Y]], [[X]]
|
||||
; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[Z]], 1073741823
|
||||
; CHECK-NEXT: ret i1 [[C]]
|
||||
;
|
||||
%y = ashr i32 %x, 31
|
||||
%z = xor i32 %y, %x
|
||||
%c = icmp ugt i32 %z, 1073741823
|
||||
ret i1 %c
|
||||
}
|
||||
|
||||
define i1 @zext_bool_and_eq0(i1 %x, i8 %y) {
|
||||
; CHECK-LABEL: @zext_bool_and_eq0(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[Y:%.*]], 1
|
||||
|
|
|
|||
Loading…
Reference in New Issue