forked from OSchip/llvm-project
[X86][SSE] Add SSE_SHUFP OpndItins
Update multi-classes to take the scheduling OpndItins instead of hard coding it. Will be reused in the AVX512 equivalents. llvm-svn: 319249
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@ -2389,43 +2389,48 @@ let Predicates = [UseSSE1] in {
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// SSE 1 & 2 - Shuffle Instructions
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// SSE 1 & 2 - Shuffle Instructions
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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let Sched = WriteFShuffle in
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def SSE_SHUFP : OpndItins<
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IIC_SSE_SHUFP, IIC_SSE_SHUFP
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>;
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/// sse12_shuffle - sse 1 & 2 fp shuffle instructions
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/// sse12_shuffle - sse 1 & 2 fp shuffle instructions
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multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
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multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
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ValueType vt, string asm, PatFrag mem_frag,
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ValueType vt, string asm, PatFrag mem_frag,
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Domain d> {
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OpndItins itins, Domain d> {
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def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
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def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, x86memop:$src2, u8imm:$src3), asm,
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(ins RC:$src1, x86memop:$src2, u8imm:$src3), asm,
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[(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
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[(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
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(i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
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(i8 imm:$src3))))], itins.rm, d>,
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Sched<[WriteFShuffleLd, ReadAfterLd]>;
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
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def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, u8imm:$src3), asm,
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(ins RC:$src1, RC:$src2, u8imm:$src3), asm,
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[(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
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[(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
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(i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
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(i8 imm:$src3))))], itins.rr, d>,
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Sched<[WriteFShuffle]>;
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Sched<[itins.Sched]>;
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}
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}
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let Predicates = [HasAVX, NoVLX] in {
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let Predicates = [HasAVX, NoVLX] in {
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defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
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defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
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"shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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"shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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loadv4f32, SSEPackedSingle>, PS, VEX_4V, VEX_WIG;
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loadv4f32, SSE_SHUFP, SSEPackedSingle>, PS, VEX_4V, VEX_WIG;
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defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
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defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
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"shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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"shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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loadv8f32, SSEPackedSingle>, PS, VEX_4V, VEX_L, VEX_WIG;
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loadv8f32, SSE_SHUFP, SSEPackedSingle>, PS, VEX_4V, VEX_L, VEX_WIG;
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defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
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defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
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"shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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"shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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loadv2f64, SSEPackedDouble>, PD, VEX_4V, VEX_WIG;
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loadv2f64, SSE_SHUFP, SSEPackedDouble>, PD, VEX_4V, VEX_WIG;
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defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
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defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
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"shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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"shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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loadv4f64, SSEPackedDouble>, PD, VEX_4V, VEX_L, VEX_WIG;
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loadv4f64, SSE_SHUFP, SSEPackedDouble>, PD, VEX_4V, VEX_L, VEX_WIG;
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}
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}
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let Constraints = "$src1 = $dst" in {
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let Constraints = "$src1 = $dst" in {
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defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
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defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
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"shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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"shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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memopv4f32, SSEPackedSingle>, PS;
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memopv4f32, SSE_SHUFP, SSEPackedSingle>, PS;
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defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
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defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
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"shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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"shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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memopv2f64, SSEPackedDouble>, PD;
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memopv2f64, SSE_SHUFP, SSEPackedDouble>, PD;
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}
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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