forked from OSchip/llvm-project
[x86][icelake][gfni]
added gfni feature recognition added intrinsics support for gfni instructions _mm_gf2p8affineinv_epi64_epi8 _mm_mask_gf2p8affineinv_epi64_epi8 _mm_maskz_gf2p8affineinv_epi64_epi8 _mm256_gf2p8affineinv_epi64_epi8 _mm256_mask_gf2p8affineinv_epi64_epi8 _mm256_maskz_gf2p8affineinv_epi64_epi8 _mm512_gf2p8affineinv_epi64_epi8 _mm512_mask_gf2p8affineinv_epi64_epi8 _mm512_maskz_gf2p8affineinv_epi64_epi8 _mm_gf2p8affine_epi64_epi8 _mm_mask_gf2p8affine_epi64_epi8 _mm_maskz_gf2p8affine_epi64_epi8 _mm256_gf2p8affine_epi64_epi8 _mm256_mask_gf2p8affine_epi64_epi8 _mm256_maskz_gf2p8affine_epi64_epi8 _mm512_gf2p8affine_epi64_epi8 _mm512_mask_gf2p8affine_epi64_epi8 _mm512_maskz_gf2p8affine_epi64_epi8 _mm_gf2p8mul_epi8 _mm_mask_gf2p8mul_epi8 _mm_maskz_gf2p8mul_epi8 _mm256_gf2p8mul_epi8 _mm256_mask_gf2p8mul_epi8 _mm256_maskz_gf2p8mul_epi8 _mm512_gf2p8mul_epi8 _mm512_mask_gf2p8mul_epi8 _mm512_maskz_gf2p8mul_epi8 matching a similar work on the backend (D40373) Differential Revision: https://reviews.llvm.org/D41582 llvm-svn: 321477
This commit is contained in:
Coby Tayree
parent
309b06cb5c
commit
f4811ebc39
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@ -439,6 +439,17 @@ TARGET_BUILTIN(__builtin_ia32_aesdec512, "V8LLiV8LLiV8LLi", "", "avx512f,vaes")
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TARGET_BUILTIN(__builtin_ia32_aesdeclast256, "V4LLiV4LLiV4LLi", "", "vaes")
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TARGET_BUILTIN(__builtin_ia32_aesdeclast512, "V8LLiV8LLiV8LLi", "", "avx512f,vaes")
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// GFNI
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TARGET_BUILTIN(__builtin_ia32_vgf2p8affineinvqb_v16qi, "V16cV16cV16cIc", "", "gfni")
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TARGET_BUILTIN(__builtin_ia32_vgf2p8affineinvqb_v32qi, "V32cV32cV32cIc", "", "avx,gfni")
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TARGET_BUILTIN(__builtin_ia32_vgf2p8affineinvqb_v64qi, "V64cV64cV64cIc", "", "avx512bw,gfni")
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TARGET_BUILTIN(__builtin_ia32_vgf2p8affineqb_v16qi, "V16cV16cV16cIc", "", "gfni")
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TARGET_BUILTIN(__builtin_ia32_vgf2p8affineqb_v32qi, "V32cV32cV32cIc", "", "avx,gfni")
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TARGET_BUILTIN(__builtin_ia32_vgf2p8affineqb_v64qi, "V64cV64cV64cIc", "", "avx512bw,gfni")
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TARGET_BUILTIN(__builtin_ia32_vgf2p8mulb_v16qi, "V16cV16cV16c", "", "gfni")
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TARGET_BUILTIN(__builtin_ia32_vgf2p8mulb_v32qi, "V32cV32cV32c", "", "avx,gfni")
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TARGET_BUILTIN(__builtin_ia32_vgf2p8mulb_v64qi, "V64cV64cV64c", "", "avx512bw,gfni")
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// CLMUL
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TARGET_BUILTIN(__builtin_ia32_pclmulqdq128, "V2LLiV2LLiV2LLiIc", "", "pclmul")
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@ -2511,6 +2511,8 @@ def mfsgsbase : Flag<["-"], "mfsgsbase">, Group<m_x86_Features_Group>;
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def mno_fsgsbase : Flag<["-"], "mno-fsgsbase">, Group<m_x86_Features_Group>;
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def mfxsr : Flag<["-"], "mfxsr">, Group<m_x86_Features_Group>;
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def mno_fxsr : Flag<["-"], "mno-fxsr">, Group<m_x86_Features_Group>;
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def mgfni : Flag<["-"], "mgfni">, Group<m_x86_Features_Group>;
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def mno_gfni : Flag<["-"], "mno-gfni">, Group<m_x86_Features_Group>;
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def mlwp : Flag<["-"], "mlwp">, Group<m_x86_Features_Group>;
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def mno_lwp : Flag<["-"], "mno-lwp">, Group<m_x86_Features_Group>;
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def mlzcnt : Flag<["-"], "mlzcnt">, Group<m_x86_Features_Group>;
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@ -133,6 +133,7 @@ bool X86TargetInfo::initFeatureMap(
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case CK_Icelake:
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setFeatureEnabledImpl(Features, "vaes", true);
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setFeatureEnabledImpl(Features, "gfni", true);
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// TODO: Add icelake features here.
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LLVM_FALLTHROUGH;
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case CK_Cannonlake:
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@ -444,7 +445,7 @@ void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
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LLVM_FALLTHROUGH;
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case SSE2:
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Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] =
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false;
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Features["gfni"] = false;
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LLVM_FALLTHROUGH;
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case SSE3:
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Features["sse3"] = false;
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@ -583,6 +584,9 @@ void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
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} else if (Name == "pclmul") {
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if (Enabled)
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setSSELevel(Features, SSE2, Enabled);
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} else if (Name == "gfni") {
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if (Enabled)
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setSSELevel(Features, SSE2, Enabled);
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} else if (Name == "avx") {
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setSSELevel(Features, AVX, Enabled);
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} else if (Name == "avx2") {
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@ -676,6 +680,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
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HasFMA = true;
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} else if (Feature == "+f16c") {
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HasF16C = true;
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} else if (Feature == "+gfni") {
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HasGFNI = true;
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} else if (Feature == "+avx512cd") {
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HasAVX512CD = true;
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} else if (Feature == "+avx512vpopcntdq") {
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@ -1009,6 +1015,9 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
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if (HasF16C)
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Builder.defineMacro("__F16C__");
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if (HasGFNI)
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Builder.defineMacro("__GFNI__");
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if (HasAVX512CD)
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Builder.defineMacro("__AVX512CD__");
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if (HasAVX512VPOPCNTDQ)
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@ -1172,6 +1181,7 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
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.Case("fma4", true)
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.Case("fsgsbase", true)
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.Case("fxsr", true)
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.Case("gfni", true)
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.Case("lwp", true)
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.Case("lzcnt", true)
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.Case("mmx", true)
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@ -1235,6 +1245,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
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.Case("fma4", XOPLevel >= FMA4)
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.Case("fsgsbase", HasFSGSBASE)
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.Case("fxsr", HasFXSR)
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.Case("gfni", HasGFNI)
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.Case("ibt", HasIBT)
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.Case("lwp", HasLWP)
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.Case("lzcnt", HasLZCNT)
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@ -50,6 +50,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
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bool HasAES = false;
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bool HasVAES = false;
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bool HasPCLMUL = false;
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bool HasGFNI = false;
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bool HasLZCNT = false;
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bool HasRDRND = false;
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bool HasFSGSBASE = false;
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@ -42,6 +42,7 @@ set(files
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fma4intrin.h
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fmaintrin.h
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fxsrintrin.h
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gfniintrin.h
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htmintrin.h
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htmxlintrin.h
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ia32intrin.h
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@ -0,0 +1,202 @@
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/*===----------------- gfniintrin.h - GFNI intrinsics ----------------------===
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*
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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*===-----------------------------------------------------------------------===
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*/
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#ifndef __IMMINTRIN_H
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#error "Never use <gfniintrin.h> directly; include <immintrin.h> instead."
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#endif
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#ifndef __GFNIINTRIN_H
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#define __GFNIINTRIN_H
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#define _mm_gf2p8affineinv_epi64_epi8(A, B, I) __extension__ ({ \
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(__m128i)__builtin_ia32_vgf2p8affineinvqb_v16qi((__v16qi)(__m128i)(A), \
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(__v16qi)(__m128i)(B), \
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(char)(I)); })
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#define _mm_mask_gf2p8affineinv_epi64_epi8(S, U, A, B, I) __extension__ ({ \
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(__m128i)__builtin_ia32_selectb_128((__mmask16)(U), \
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(__v16qi)_mm_gf2p8affineinv_epi64_epi8(A, B, I), \
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(__v16qi)(__m128i)(S)); })
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#define _mm_maskz_gf2p8affineinv_epi64_epi8(U, A, B, I) __extension__ ({ \
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(__m128i)_mm_mask_gf2p8affineinv_epi64_epi8((__m128i)_mm_setzero_si128(), \
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U, A, B, I); })
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#define _mm256_gf2p8affineinv_epi64_epi8(A, B, I) __extension__ ({ \
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(__m256i)__builtin_ia32_vgf2p8affineinvqb_v32qi((__v32qi)(__m256i)(A), \
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(__v32qi)(__m256i)(B), \
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(char)(I)); })
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#define _mm256_mask_gf2p8affineinv_epi64_epi8(S, U, A, B, I) __extension__ ({ \
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(__m256i)__builtin_ia32_selectb_256((__mmask32)(U), \
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(__v32qi)_mm256_gf2p8affineinv_epi64_epi8(A, B, I), \
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(__v32qi)(__m256i)(S)); })
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#define _mm256_maskz_gf2p8affineinv_epi64_epi8(U, A, B, I) __extension__ ({ \
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(__m256i)_mm256_mask_gf2p8affineinv_epi64_epi8((__m256i)_mm256_setzero_si256(), \
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U, A, B, I); })
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#define _mm512_gf2p8affineinv_epi64_epi8(A, B, I) __extension__ ({ \
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(__m512i)__builtin_ia32_vgf2p8affineinvqb_v64qi((__v64qi)(__m512i)(A), \
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(__v64qi)(__m512i)(B), \
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(char)(I)); })
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#define _mm512_mask_gf2p8affineinv_epi64_epi8(S, U, A, B, I) __extension__ ({ \
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(__m512i)__builtin_ia32_selectb_512((__mmask64)(U), \
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(__v64qi)_mm512_gf2p8affineinv_epi64_epi8(A, B, I), \
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(__v64qi)(__m512i)(S)); })
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#define _mm512_maskz_gf2p8affineinv_epi64_epi8(U, A, B, I) __extension__ ({ \
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(__m512i)_mm512_mask_gf2p8affineinv_epi64_epi8((__m512i)_mm512_setzero_qi(), \
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U, A, B, I); })
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#define _mm_gf2p8affine_epi64_epi8(A, B, I) __extension__ ({ \
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(__m128i)__builtin_ia32_vgf2p8affineqb_v16qi((__v16qi)(__m128i)(A), \
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(__v16qi)(__m128i)(B), \
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(char)(I)); })
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#define _mm_mask_gf2p8affine_epi64_epi8(S, U, A, B, I) __extension__ ({ \
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(__m128i)__builtin_ia32_selectb_128((__mmask16)(U), \
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(__v16qi)_mm_gf2p8affine_epi64_epi8(A, B, I), \
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(__v16qi)(__m128i)(S)); })
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#define _mm_maskz_gf2p8affine_epi64_epi8(U, A, B, I) __extension__ ({ \
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(__m128i)_mm_mask_gf2p8affine_epi64_epi8((__m128i)_mm_setzero_si128(), \
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U, A, B, I); })
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#define _mm256_gf2p8affine_epi64_epi8(A, B, I) __extension__ ({ \
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(__m256i)__builtin_ia32_vgf2p8affineqb_v32qi((__v32qi)(__m256i)(A), \
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(__v32qi)(__m256i)(B), \
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(char)(I)); })
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#define _mm256_mask_gf2p8affine_epi64_epi8(S, U, A, B, I) __extension__ ({ \
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(__m256i)__builtin_ia32_selectb_256((__mmask32)(U), \
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(__v32qi)_mm256_gf2p8affine_epi64_epi8(A, B, I), \
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(__v32qi)(__m256i)(S)); })
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#define _mm256_maskz_gf2p8affine_epi64_epi8(U, A, B, I) __extension__ ({ \
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(__m256i)_mm256_mask_gf2p8affine_epi64_epi8((__m256i)_mm256_setzero_si256(), \
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U, A, B, I); })
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#define _mm512_gf2p8affine_epi64_epi8(A, B, I) __extension__ ({ \
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(__m512i)__builtin_ia32_vgf2p8affineqb_v64qi((__v64qi)(__m512i)(A), \
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(__v64qi)(__m512i)(B), \
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(char)(I)); })
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#define _mm512_mask_gf2p8affine_epi64_epi8(S, U, A, B, I) __extension__ ({ \
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(__m512i)__builtin_ia32_selectb_512((__mmask64)(U), \
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(__v64qi)_mm512_gf2p8affine_epi64_epi8(A, B, I), \
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(__v64qi)(__m512i)(S)); })
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#define _mm512_maskz_gf2p8affine_epi64_epi8(U, A, B, I) __extension__ ({ \
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(__m512i)_mm512_mask_gf2p8affine_epi64_epi8((__m512i)_mm512_setzero_qi(), \
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U, A, B, I); })
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/* Default attributes for simple form (no masking). */
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#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("gfni")))
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/* Default attributes for ZMM forms. */
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#define __DEFAULT_FN_ATTRS_F __attribute__((__always_inline__, __nodebug__, __target__("avx512bw,gfni")))
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/* Default attributes for VLX forms. */
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#define __DEFAULT_FN_ATTRS_VL __attribute__((__always_inline__, __nodebug__, __target__("avx512bw,avx512vl,gfni")))
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static __inline__ __m128i __DEFAULT_FN_ATTRS
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_mm_gf2p8mul_epi8(__m128i __A, __m128i __B)
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{
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return (__m128i) __builtin_ia32_vgf2p8mulb_v16qi((__v16qi) __A,
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(__v16qi) __B);
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}
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static __inline__ __m128i __DEFAULT_FN_ATTRS_VL
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_mm_mask_gf2p8mul_epi8(__m128i __S, __mmask16 __U, __m128i __A, __m128i __B)
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{
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return (__m128i) __builtin_ia32_selectb_128(__U,
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(__v16qi) _mm_gf2p8mul_epi8(__A, __B),
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(__v16qi) __S);
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}
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static __inline__ __m128i __DEFAULT_FN_ATTRS_VL
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_mm_maskz_gf2p8mul_epi8(__mmask16 __U, __m128i __A, __m128i __B)
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{
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return _mm_mask_gf2p8mul_epi8((__m128i)_mm_setzero_si128(),
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__U, __A, __B);
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}
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static __inline__ __m256i __DEFAULT_FN_ATTRS
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_mm256_gf2p8mul_epi8(__m256i __A, __m256i __B)
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{
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return (__m256i) __builtin_ia32_vgf2p8mulb_v32qi((__v32qi) __A,
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(__v32qi) __B);
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}
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static __inline__ __m256i __DEFAULT_FN_ATTRS_VL
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_mm256_mask_gf2p8mul_epi8(__m256i __S, __mmask32 __U, __m256i __A, __m256i __B)
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{
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return (__m256i) __builtin_ia32_selectb_256(__U,
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(__v32qi) _mm256_gf2p8mul_epi8(__A, __B),
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(__v32qi) __S);
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}
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static __inline__ __m256i __DEFAULT_FN_ATTRS_VL
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_mm256_maskz_gf2p8mul_epi8(__mmask32 __U, __m256i __A, __m256i __B)
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{
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return _mm256_mask_gf2p8mul_epi8((__m256i)_mm256_setzero_si256(),
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__U, __A, __B);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS_F
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_mm512_gf2p8mul_epi8(__m512i __A, __m512i __B)
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{
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return (__m512i) __builtin_ia32_vgf2p8mulb_v64qi((__v64qi) __A,
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(__v64qi) __B);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS_F
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_mm512_mask_gf2p8mul_epi8(__m512i __S, __mmask64 __U, __m512i __A, __m512i __B)
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{
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return (__m512i) __builtin_ia32_selectb_512(__U,
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(__v64qi) _mm512_gf2p8mul_epi8(__A, __B),
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(__v64qi) __S);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS_F
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_mm512_maskz_gf2p8mul_epi8(__mmask64 __U, __m512i __A, __m512i __B)
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{
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return _mm512_mask_gf2p8mul_epi8((__m512i)_mm512_setzero_qi(),
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__U, __A, __B);
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}
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#undef __DEFAULT_FN_ATTRS
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#undef __DEFAULT_FN_ATTRS_F
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#undef __DEFAULT_FN_ATTRS_VL
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#endif // __GFNIINTRIN_H
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@ -212,6 +212,10 @@ _mm256_cvtph_ps(__m128i __a)
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#include <vaesintrin.h>
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#endif
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|
||||
#if !defined(_MSC_VER) || __has_feature(modules) || defined(__GFNI__)
|
||||
#include <gfniintrin.h>
|
||||
#endif
|
||||
|
||||
#if !defined(_MSC_VER) || __has_feature(modules) || defined(__RDRND__)
|
||||
static __inline__ int __attribute__((__always_inline__, __nodebug__, __target__("rdrnd")))
|
||||
_rdrand16_step(unsigned short *__p)
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@ int __attribute__((target("arch=lakemont,mmx"))) lake(int a) { return 4; }
|
|||
// CHECK: lake{{.*}} #7
|
||||
// CHECK: #0 = {{.*}}"target-cpu"="i686" "target-features"="+x87"
|
||||
// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"
|
||||
// CHECK: #2 = {{.*}}"target-cpu"="i686" "target-features"="+x87,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vl,-avx512vpopcntdq,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-xop,-xsave,-xsaveopt"
|
||||
// CHECK: #2 = {{.*}}"target-cpu"="i686" "target-features"="+x87,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vl,-avx512vpopcntdq,-f16c,-fma,-fma4,-gfni,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-xop,-xsave,-xsaveopt"
|
||||
// CHECK: #3 = {{.*}}"target-cpu"="i686" "target-features"="+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87"
|
||||
// CHECK: #4 = {{.*}}"target-cpu"="i686" "target-features"="+x87,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vl,-avx512vpopcntdq,-f16c,-fma,-fma4,-sse4.1,-sse4.2,-vaes,-xop,-xsave,-xsaveopt"
|
||||
// CHECK: #5 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt,-aes,-vaes"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,182 @@
|
|||
// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +gfni -emit-llvm -o - | FileCheck %s --check-prefix SSE
|
||||
// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-apple-darwin -DAVX -target-feature +gfni -target-feature +avx -emit-llvm -o - | FileCheck %s --check-prefixes SSE,AVX
|
||||
// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-apple-darwin -DAVX512 -target-feature +gfni -target-feature +avx512bw -target-feature +avx512vl -emit-llvm -o - | FileCheck %s --check-prefixes SSE,AVX,AVX512
|
||||
|
||||
#include <immintrin.h>
|
||||
|
||||
__m128i test_mm_gf2p8affineinv_epi64_epi8(__m128i A, __m128i B) {
|
||||
// SSE-LABEL: @test_mm_gf2p8affineinv_epi64_epi8
|
||||
// SSE: @llvm.x86.vgf2p8affineinvqb.128
|
||||
return _mm_gf2p8affineinv_epi64_epi8(A, B, 1);
|
||||
}
|
||||
|
||||
__m128i test_mm_gf2p8affine_epi64_epi8(__m128i A, __m128i B) {
|
||||
// SSE-LABEL: @test_mm_gf2p8affine_epi64_epi8
|
||||
// SSE: @llvm.x86.vgf2p8affineqb.128
|
||||
return _mm_gf2p8affine_epi64_epi8(A, B, 1);
|
||||
}
|
||||
|
||||
__m128i test_mm_gf2p8mul_epi8(__m128i A, __m128i B) {
|
||||
// SSE-LABEL: @test_mm_gf2p8mul_epi8
|
||||
// SSE: @llvm.x86.vgf2p8mulb.128
|
||||
return _mm_gf2p8mul_epi8(A, B);
|
||||
}
|
||||
|
||||
#if defined(AVX) || defined(AVX512)
|
||||
__m256i test_mm256_gf2p8affineinv_epi64_epi8(__m256i A, __m256i B) {
|
||||
// AVX-LABEL: @test_mm256_gf2p8affineinv_epi64_epi8
|
||||
// AVX: @llvm.x86.vgf2p8affineinvqb.256
|
||||
return _mm256_gf2p8affineinv_epi64_epi8(A, B, 1);
|
||||
}
|
||||
|
||||
__m256i test_mm256_gf2p8affine_epi64_epi8(__m256i A, __m256i B) {
|
||||
// AVX-LABEL: @test_mm256_gf2p8affine_epi64_epi8
|
||||
// AVX: @llvm.x86.vgf2p8affineqb.256
|
||||
return _mm256_gf2p8affine_epi64_epi8(A, B, 1);
|
||||
}
|
||||
|
||||
__m256i test_mm256_gf2p8mul_epi8(__m256i A, __m256i B) {
|
||||
// AVX-LABEL: @test_mm256_gf2p8mul_epi8
|
||||
// AVX: @llvm.x86.vgf2p8mulb.256
|
||||
return _mm256_gf2p8mul_epi8(A, B);
|
||||
}
|
||||
#endif // AVX
|
||||
|
||||
#ifdef AVX512
|
||||
__m512i test_mm512_gf2p8affineinv_epi64_epi8(__m512i A, __m512i B) {
|
||||
// AVX512-LABEL: @test_mm512_gf2p8affineinv_epi64_epi8
|
||||
// AVX512: @llvm.x86.vgf2p8affineinvqb.512
|
||||
return _mm512_gf2p8affineinv_epi64_epi8(A, B, 1);
|
||||
}
|
||||
|
||||
__m512i test_mm512_mask_gf2p8affineinv_epi64_epi8(__m512i S, __mmask64 U, __m512i A, __m512i B) {
|
||||
// AVX512-LABEL: @test_mm512_mask_gf2p8affineinv_epi64_epi8
|
||||
// AVX512: @llvm.x86.vgf2p8affineinvqb.512
|
||||
// AVX512: select <64 x i1> %{{[0-9]+}}, <64 x i8> %{{[0-9]+}}, <64 x i8> {{.*}}
|
||||
return _mm512_mask_gf2p8affineinv_epi64_epi8(S, U, A, B, 1);
|
||||
}
|
||||
|
||||
__m512i test_mm512_maskz_gf2p8affineinv_epi64_epi8(__mmask64 U, __m512i A, __m512i B) {
|
||||
// AVX512-LABEL: @test_mm512_maskz_gf2p8affineinv_epi64_epi8
|
||||
// AVX512: @llvm.x86.vgf2p8affineinvqb.512
|
||||
// AVX512: select <64 x i1> %{{[0-9]+}}, <64 x i8> %{{[0-9]+}}, <64 x i8> {{.*}}
|
||||
return _mm512_maskz_gf2p8affineinv_epi64_epi8(U, A, B, 1);
|
||||
}
|
||||
|
||||
__m256i test_mm256_mask_gf2p8affineinv_epi64_epi8(__m256i S, __mmask32 U, __m256i A, __m256i B) {
|
||||
// AVX256-LABEL: @test_mm256_mask_gf2p8affineinv_epi64_epi8
|
||||
// AVX256: @llvm.x86.vgf2p8affineinvqb.256
|
||||
// AVX256: select <32 x i1> %{{[0-9]+}}, <32 x i8> %{{[0-9]+}}, <32 x i8> {{.*}}
|
||||
return _mm256_mask_gf2p8affineinv_epi64_epi8(S, U, A, B, 1);
|
||||
}
|
||||
|
||||
__m256i test_mm256_maskz_gf2p8affineinv_epi64_epi8(__mmask32 U, __m256i A, __m256i B) {
|
||||
// AVX256-LABEL: @test_mm256_maskz_gf2p8affineinv_epi64_epi8
|
||||
// AVX256: @llvm.x86.vgf2p8affineinvqb.256
|
||||
// AVX256: select <32 x i1> %{{[0-9]+}}, <32 x i8> %{{[0-9]+}}, <32 x i8> {{.*}}
|
||||
return _mm256_maskz_gf2p8affineinv_epi64_epi8(U, A, B, 1);
|
||||
}
|
||||
|
||||
__m128i test_mm_mask_gf2p8affineinv_epi64_epi8(__m128i S, __mmask16 U, __m128i A, __m128i B) {
|
||||
// AVX512-LABEL: @test_mm_mask_gf2p8affineinv_epi64_epi8
|
||||
// AVX512: @llvm.x86.vgf2p8affineinvqb.128
|
||||
// AVX512: select <16 x i1> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i8> {{.*}}
|
||||
return _mm_mask_gf2p8affineinv_epi64_epi8(S, U, A, B, 1);
|
||||
}
|
||||
|
||||
__m128i test_mm_maskz_gf2p8affineinv_epi64_epi8(__mmask16 U, __m128i A, __m128i B) {
|
||||
// AVX512-LABEL: @test_mm_maskz_gf2p8affineinv_epi64_epi8
|
||||
// AVX512: @llvm.x86.vgf2p8affineinvqb.128
|
||||
// AVX512: select <16 x i1> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i8> {{.*}}
|
||||
return _mm_maskz_gf2p8affineinv_epi64_epi8(U, A, B, 1);
|
||||
}
|
||||
|
||||
__m512i test_mm512_gf2p8affine_epi64_epi8(__m512i A, __m512i B) {
|
||||
// AVX512-LABEL: @test_mm512_gf2p8affine_epi64_epi8
|
||||
// AVX512: @llvm.x86.vgf2p8affineqb.512
|
||||
return _mm512_gf2p8affine_epi64_epi8(A, B, 1);
|
||||
}
|
||||
|
||||
__m512i test_mm512_mask_gf2p8affine_epi64_epi8(__m512i S, __mmask64 U, __m512i A, __m512i B) {
|
||||
// AVX512-LABEL: @test_mm512_mask_gf2p8affine_epi64_epi8
|
||||
// AVX512: @llvm.x86.vgf2p8affineqb.512
|
||||
// AVX512: select <64 x i1> %{{[0-9]+}}, <64 x i8> %{{[0-9]+}}, <64 x i8> {{.*}}
|
||||
return _mm512_mask_gf2p8affine_epi64_epi8(S, U, A, B, 1);
|
||||
}
|
||||
|
||||
__m512i test_mm512_maskz_gf2p8affine_epi64_epi8(__mmask64 U, __m512i A, __m512i B) {
|
||||
// AVX512-LABEL: @test_mm512_maskz_gf2p8affine_epi64_epi8
|
||||
// AVX512: @llvm.x86.vgf2p8affineqb.512
|
||||
// AVX512: select <64 x i1> %{{[0-9]+}}, <64 x i8> %{{[0-9]+}}, <64 x i8> {{.*}}
|
||||
return _mm512_maskz_gf2p8affine_epi64_epi8(U, A, B, 1);
|
||||
}
|
||||
|
||||
__m256i test_mm256_mask_gf2p8affine_epi64_epi8(__m256i S, __mmask32 U, __m256i A, __m256i B) {
|
||||
// AVX256-LABEL: @test_mm256_mask_gf2p8affine_epi64_epi8
|
||||
// AVX256: @llvm.x86.vgf2p8affineqb.256
|
||||
// AVX256: select <32 x i1> %{{[0-9]+}}, <32 x i8> %{{[0-9]+}}, <32 x i8> {{.*}}
|
||||
return _mm256_mask_gf2p8affine_epi64_epi8(S, U, A, B, 1);
|
||||
}
|
||||
|
||||
__m256i test_mm256_maskz_gf2p8affine_epi64_epi8(__mmask32 U, __m256i A, __m256i B) {
|
||||
// AVX256-LABEL: @test_mm256_maskz_gf2p8affine_epi64_epi8
|
||||
// AVX256: @llvm.x86.vgf2p8affineqb.256
|
||||
// AVX256: select <32 x i1> %{{[0-9]+}}, <32 x i8> %{{[0-9]+}}, <32 x i8> {{.*}}
|
||||
return _mm256_maskz_gf2p8affine_epi64_epi8(U, A, B, 1);
|
||||
}
|
||||
|
||||
__m128i test_mm_mask_gf2p8affine_epi64_epi8(__m128i S, __mmask16 U, __m128i A, __m128i B) {
|
||||
// AVX512-LABEL: @test_mm_mask_gf2p8affine_epi64_epi8
|
||||
// AVX512: @llvm.x86.vgf2p8affineqb.128
|
||||
// AVX512: select <16 x i1> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i8> {{.*}}
|
||||
return _mm_mask_gf2p8affine_epi64_epi8(S, U, A, B, 1);
|
||||
}
|
||||
|
||||
__m128i test_mm_maskz_gf2p8affine_epi64_epi8(__mmask16 U, __m128i A, __m128i B) {
|
||||
// AVX512-LABEL: @test_mm_maskz_gf2p8affine_epi64_epi8
|
||||
// AVX512: @llvm.x86.vgf2p8affineqb.128
|
||||
// AVX512: select <16 x i1> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i8> {{.*}}
|
||||
return _mm_maskz_gf2p8affine_epi64_epi8(U, A, B, 1);
|
||||
}
|
||||
|
||||
__m512i test_mm512_gf2p8mul_epi8(__m512i A, __m512i B) {
|
||||
// AVX512-LABEL: @test_mm512_gf2p8mul_epi8
|
||||
// AVX512: @llvm.x86.vgf2p8mulb.512
|
||||
return _mm512_gf2p8mul_epi8(A, B);
|
||||
}
|
||||
|
||||
__m512i test_mm512_mask_gf2p8mul_epi8(__m512i S, __mmask64 U, __m512i A, __m512i B) {
|
||||
// AVX512-LABEL: @test_mm512_mask_gf2p8mul_epi8
|
||||
// AVX512: @llvm.x86.vgf2p8mulb.512
|
||||
// AVX512: select <64 x i1> %{{[0-9]+}}, <64 x i8> %{{[0-9]+}}, <64 x i8> {{.*}}
|
||||
return _mm512_mask_gf2p8mul_epi8(S, U, A, B);
|
||||
}
|
||||
|
||||
__m512i test_mm512_maskz_gf2p8mul_epi8(__mmask64 U, __m512i A, __m512i B) {
|
||||
// AVX512-LABEL: @test_mm512_maskz_gf2p8mul_epi8
|
||||
// AVX512: @llvm.x86.vgf2p8mulb.512
|
||||
// AVX512: select <64 x i1> %{{[0-9]+}}, <64 x i8> %{{[0-9]+}}, <64 x i8> {{.*}}
|
||||
return _mm512_maskz_gf2p8mul_epi8(U, A, B);
|
||||
}
|
||||
|
||||
__m256i test_mm256_mask_gf2p8mul_epi8(__m256i S, __mmask32 U, __m256i A, __m256i B) {
|
||||
// AVX256-LABEL: @test_mm256_mask_gf2p8mul_epi8
|
||||
// AVX256: @llvm.x86.vgf2p8mulb.256
|
||||
// AVX256: select <32 x i1> %{{[0-9]+}}, <32 x i8> %{{[0-9]+}}, <32 x i8> {{.*}}
|
||||
return _mm256_mask_gf2p8mul_epi8(S, U, A, B);
|
||||
}
|
||||
|
||||
__m256i test_mm256_maskz_gf2p8mul_epi8(__mmask32 U, __m256i A, __m256i B) {
|
||||
// AVX256-LABEL: @test_mm256_maskz_gf2p8mul_epi8
|
||||
// AVX256: @llvm.x86.vgf2p8mulb.256
|
||||
// AVX256: select <32 x i1> %{{[0-9]+}}, <32 x i8> %{{[0-9]+}}, <32 x i8> {{.*}}
|
||||
return _mm256_maskz_gf2p8mul_epi8(U, A, B);
|
||||
}
|
||||
|
||||
__m128i test_mm_mask_gf2p8mul_epi8(__m128i S, __mmask16 U, __m128i A, __m128i B) {
|
||||
// AVX512-LABEL: @test_mm_mask_gf2p8mul_epi8
|
||||
// AVX512: @llvm.x86.vgf2p8mulb.128
|
||||
// AVX512: select <16 x i1> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i8> {{.*}}
|
||||
return _mm_mask_gf2p8mul_epi8(S, U, A, B);
|
||||
}
|
||||
#endif // AVX512
|
||||
|
|
@ -100,3 +100,8 @@
|
|||
// VAES: "-target-feature" "+vaes"
|
||||
// NO-VAES: "-target-feature" "-vaes"
|
||||
|
||||
// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mgfni %s -### -o %t.o 2>&1 | FileCheck -check-prefix=GFNI %s
|
||||
// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-gfni %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-GFNI %s
|
||||
// GFNI: "-target-feature" "+gfni"
|
||||
// NO-GFNI: "-target-feature" "-gfni
|
||||
|
||||
|
|
|
|||
|
|
@ -1063,6 +1063,7 @@
|
|||
// CHECK_ICL_M32: #define __CLFLUSHOPT__ 1
|
||||
// CHECK_ICL_M32: #define __F16C__ 1
|
||||
// CHECK_ICL_M32: #define __FMA__ 1
|
||||
// CHECK_ICL_M32: #define __GFNI__ 1
|
||||
// CHECK_ICL_M32: #define __LZCNT__ 1
|
||||
// CHECK_ICL_M32: #define __MMX__ 1
|
||||
// CHECK_ICL_M32: #define __MPX__ 1
|
||||
|
|
@ -1109,6 +1110,7 @@
|
|||
// CHECK_ICL_M64: #define __CLFLUSHOPT__ 1
|
||||
// CHECK_ICL_M64: #define __F16C__ 1
|
||||
// CHECK_ICL_M64: #define __FMA__ 1
|
||||
// CHECK_ICL_M64: #define __GFNI__ 1
|
||||
// CHECK_ICL_M64: #define __LZCNT__ 1
|
||||
// CHECK_ICL_M64: #define __MMX__ 1
|
||||
// CHECK_ICL_M64: #define __MPX__ 1
|
||||
|
|
|
|||
|
|
@ -379,3 +379,8 @@
|
|||
// VAESNOAES-NOT: #define __AES__ 1
|
||||
// VAESNOAES-NOT: #define __VAES__ 1
|
||||
|
||||
// RUN: %clang -target i386-unknown-unknown -march=atom -mgfni -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=GFNI %s
|
||||
|
||||
// GFNI: #define __GFNI__ 1
|
||||
// GFNI: #define __SSE2__ 1
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue