forked from OSchip/llvm-project
Avoid partial CPSR dependency from loop backedges. rdar://10357570
llvm-svn: 143145
This commit is contained in:
Evan Cheng
parent
a054790390
commit
f4807a19e8
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@ -146,7 +146,8 @@ namespace {
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/// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable.
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DenseMap<unsigned, unsigned> ReduceOpcodeMap;
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bool canAddPseudoFlagDep(MachineInstr *Def, MachineInstr *Use);
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bool canAddPseudoFlagDep(MachineInstr *Def, MachineInstr *Use,
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bool IsSelfLoop);
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bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
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bool is2Addr, ARMCC::CondCodes Pred,
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@ -157,19 +158,21 @@ namespace {
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bool ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
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const ReduceEntry &Entry, bool LiveCPSR,
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MachineInstr *CPSRDef);
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MachineInstr *CPSRDef, bool IsSelfLoop);
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/// ReduceTo2Addr - Reduce a 32-bit instruction to a 16-bit two-address
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/// instruction.
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bool ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
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const ReduceEntry &Entry,
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bool LiveCPSR, MachineInstr *CPSRDef);
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bool LiveCPSR, MachineInstr *CPSRDef,
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bool IsSelfLoop);
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/// ReduceToNarrow - Reduce a 32-bit instruction to a 16-bit
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/// non-two-address instruction.
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bool ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
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const ReduceEntry &Entry,
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bool LiveCPSR, MachineInstr *CPSRDef);
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bool LiveCPSR, MachineInstr *CPSRDef,
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bool IsSelfLoop);
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/// ReduceMBB - Reduce width of instructions in the specified basic block.
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bool ReduceMBB(MachineBasicBlock &MBB);
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@ -210,10 +213,17 @@ static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) {
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/// In this case it would have been ok to narrow the mul.w to muls since there
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/// are indirect RAW dependency between the muls and the mul.w
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bool
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Thumb2SizeReduce::canAddPseudoFlagDep(MachineInstr *Def, MachineInstr *Use) {
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if (!Def || !STI->avoidCPSRPartialUpdate())
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Thumb2SizeReduce::canAddPseudoFlagDep(MachineInstr *Def, MachineInstr *Use,
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bool FirstInSelfLoop) {
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// FIXME: Disable check for -Oz (aka OptimizeForSizeHarder).
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if (!STI->avoidCPSRPartialUpdate())
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return false;
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if (!Def)
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// If this BB loops back to itself, conservatively avoid narrowing the
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// first instruction that does partial flag update.
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return FirstInSelfLoop;
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SmallSet<unsigned, 2> Defs;
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for (unsigned i = 0, e = Def->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = Def->getOperand(i);
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@ -476,15 +486,16 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
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bool
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Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
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const ReduceEntry &Entry,
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bool LiveCPSR, MachineInstr *CPSRDef) {
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bool LiveCPSR, MachineInstr *CPSRDef,
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bool IsSelfLoop) {
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unsigned Opc = MI->getOpcode();
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if (Opc == ARM::t2ADDri) {
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// If the source register is SP, try to reduce to tADDrSPi, otherwise
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// it's a normal reduce.
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if (MI->getOperand(1).getReg() != ARM::SP) {
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if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef))
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if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop))
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return true;
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return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef);
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return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop);
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}
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// Try to reduce to tADDrSPi.
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unsigned Imm = MI->getOperand(2).getImm();
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@ -535,12 +546,12 @@ Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
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switch (Opc) {
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default: break;
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case ARM::t2ADDSri: {
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if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef))
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if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop))
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return true;
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// fallthrough
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}
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case ARM::t2ADDSrr:
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return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef);
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return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop);
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}
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}
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break;
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@ -552,13 +563,13 @@ Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
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case ARM::t2UXTB:
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case ARM::t2UXTH:
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if (MI->getOperand(2).getImm() == 0)
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return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef);
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return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop);
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break;
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case ARM::t2MOVi16:
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// Can convert only 'pure' immediate operands, not immediates obtained as
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// globals' addresses.
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if (MI->getOperand(1).isImm())
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return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef);
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return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop);
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break;
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case ARM::t2CMPrr: {
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// Try to reduce to the lo-reg only version first. Why there are two
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@ -568,9 +579,9 @@ Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
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// source insn opcode. So for now, we hack a local entry record to use.
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static const ReduceEntry NarrowEntry =
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{ ARM::t2CMPrr,ARM::tCMPr, 0, 0, 0, 1, 1,2, 0, 0,1 };
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if (ReduceToNarrow(MBB, MI, NarrowEntry, LiveCPSR, CPSRDef))
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if (ReduceToNarrow(MBB, MI, NarrowEntry, LiveCPSR, CPSRDef, IsSelfLoop))
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return true;
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return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef);
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return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop);
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}
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}
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return false;
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@ -579,7 +590,8 @@ Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
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bool
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Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
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const ReduceEntry &Entry,
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bool LiveCPSR, MachineInstr *CPSRDef) {
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bool LiveCPSR, MachineInstr *CPSRDef,
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bool IsSelfLoop) {
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if (ReduceLimit2Addr != -1 && ((int)Num2Addrs >= ReduceLimit2Addr))
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return false;
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@ -637,7 +649,7 @@ Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
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// Avoid adding a false dependency on partial flag update by some 16-bit
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// instructions which has the 's' bit set.
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if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC &&
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canAddPseudoFlagDep(CPSRDef, MI))
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canAddPseudoFlagDep(CPSRDef, MI, IsSelfLoop))
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return false;
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// Add the 16-bit instruction.
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@ -674,7 +686,8 @@ Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
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bool
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Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
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const ReduceEntry &Entry,
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bool LiveCPSR, MachineInstr *CPSRDef) {
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bool LiveCPSR, MachineInstr *CPSRDef,
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bool IsSelfLoop) {
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if (ReduceLimit != -1 && ((int)NumNarrows >= ReduceLimit))
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return false;
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@ -727,7 +740,7 @@ Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
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// Avoid adding a false dependency on partial flag update by some 16-bit
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// instructions which has the 's' bit set.
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if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC &&
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canAddPseudoFlagDep(CPSRDef, MI))
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canAddPseudoFlagDep(CPSRDef, MI, IsSelfLoop))
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return false;
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// Add the 16-bit instruction.
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@ -818,6 +831,9 @@ bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
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bool LiveCPSR = MBB.isLiveIn(ARM::CPSR);
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MachineInstr *CPSRDef = 0;
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// If this BB loops back to itself, conservatively avoid narrowing the
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// first instruction that does partial flag update.
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bool IsSelfLoop = MBB.isSuccessor(&MBB);
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MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
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MachineBasicBlock::iterator NextMII;
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for (; MII != E; MII = NextMII) {
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@ -832,7 +848,7 @@ bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
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const ReduceEntry &Entry = ReduceTable[OPI->second];
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// Ignore "special" cases for now.
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if (Entry.Special) {
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if (ReduceSpecial(MBB, MI, Entry, LiveCPSR, CPSRDef)) {
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if (ReduceSpecial(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop)) {
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Modified = true;
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MachineBasicBlock::iterator I = prior(NextMII);
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MI = &*I;
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@ -842,7 +858,7 @@ bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
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// Try to transform to a 16-bit two-address instruction.
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if (Entry.NarrowOpc2 &&
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ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef)) {
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ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop)) {
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Modified = true;
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MachineBasicBlock::iterator I = prior(NextMII);
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MI = &*I;
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@ -851,7 +867,7 @@ bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
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// Try to transform to a 16-bit non-two-address instruction.
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if (Entry.NarrowOpc1 &&
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ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef)) {
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ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop)) {
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Modified = true;
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MachineBasicBlock::iterator I = prior(NextMII);
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MI = &*I;
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@ -861,12 +877,15 @@ bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
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ProcessNext:
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bool DefCPSR = false;
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LiveCPSR = UpdateCPSRDef(*MI, LiveCPSR, DefCPSR);
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if (MI->getDesc().isCall())
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if (MI->getDesc().isCall()) {
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// Calls don't really set CPSR.
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CPSRDef = 0;
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else if (DefCPSR)
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IsSelfLoop = false;
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} else if (DefCPSR) {
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// This is the last CPSR defining instruction.
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CPSRDef = MI;
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IsSelfLoop = false;
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}
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}
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return Modified;
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@ -3,9 +3,9 @@
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; dependency) when it isn't dependent on last CPSR defining instruction.
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; rdar://8928208
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define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
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define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
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entry:
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; CHECK: t:
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; CHECK: t1:
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; CHECK: muls [[REG:(r[0-9]+)]], r2, r3
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; CHECK-NEXT: mul [[REG2:(r[0-9]+)]], r0, r1
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; CHECK-NEXT: muls r0, [[REG2]], [[REG]]
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@ -14,3 +14,37 @@ define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
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%2 = mul nsw i32 %0, %1
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ret i32 %2
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}
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; Avoid partial CPSR dependency via loop backedge.
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; rdar://10357570
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define void @t2(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind {
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entry:
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; CHECK: t2:
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%tobool7 = icmp eq i32* %ptr2, null
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br i1 %tobool7, label %while.end, label %while.body
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while.body:
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; CHECK: while.body
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; CHECK: mul r{{[0-9]+}}
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; CHECK-NOT: muls
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%ptr1.addr.09 = phi i32* [ %add.ptr, %while.body ], [ %ptr1, %entry ]
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%ptr2.addr.08 = phi i32* [ %incdec.ptr, %while.body ], [ %ptr2, %entry ]
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%0 = load i32* %ptr1.addr.09, align 4
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%arrayidx1 = getelementptr inbounds i32* %ptr1.addr.09, i32 1
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%1 = load i32* %arrayidx1, align 4
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%arrayidx3 = getelementptr inbounds i32* %ptr1.addr.09, i32 2
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%2 = load i32* %arrayidx3, align 4
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%arrayidx4 = getelementptr inbounds i32* %ptr1.addr.09, i32 3
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%3 = load i32* %arrayidx4, align 4
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%add.ptr = getelementptr inbounds i32* %ptr1.addr.09, i32 4
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%mul = mul i32 %1, %0
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%mul5 = mul i32 %mul, %2
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%mul6 = mul i32 %mul5, %3
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store i32 %mul6, i32* %ptr2.addr.08, align 4
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%incdec.ptr = getelementptr inbounds i32* %ptr2.addr.08, i32 -1
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%tobool = icmp eq i32* %incdec.ptr, null
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br i1 %tobool, label %while.end, label %while.body
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while.end:
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ret void
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}
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