forked from OSchip/llvm-project
[ELF] Fix 3 tests after D56828
arm-plt-reloc.s arm-thumb-plt-reloc.s: update offset calculations pack-dyn-relocs-loop.s: this test is very sensitive to exact section offsets and sizes. If we comment out the following two lines in SyntheticSections.cpp, we should reproduce `ld.lld: error: thunk creation not converged` caused by oscillation of the section size. if (RelocData.size() < OldSize) RelocData.append(OldSize - RelocData.size(), 0); Use -z norelro to counteract the layout change (to be more specific, we have to place .dynamic below .foo so that offset(foo) remains 0x10004) llvm-svn: 356229
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@ -50,7 +50,7 @@ _start:
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// DSO-NEXT: Disassembly of section .plt:
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// DSO-NEXT: $a:
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// DSO-NEXT: 1020: 04 e0 2d e5 str lr, [sp, #-4]!
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// (0x1024 + 8) + (0 RoR 12) + (0 RoR 20) + (0xfdc) = 0x2008 = .got.plt[3]
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// (0x1024 + 8) + (0 RoR 12) + 4096 + (0xfdc) = 0x3008 = .got.plt[3]
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// DSO-NEXT: 1024: 00 e6 8f e2 add lr, pc, #0, #12
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// DSO-NEXT: 1028: 01 ea 8e e2 add lr, lr, #4096
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// DSO-NEXT: 102c: dc ff be e5 ldr pc, [lr, #4060]!
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@ -60,21 +60,21 @@ _start:
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// DSO-NEXT: 1038: d4 d4 d4 d4 .word 0xd4d4d4d4
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// DSO-NEXT: 103c: d4 d4 d4 d4 .word 0xd4d4d4d4
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// DSO: $a:
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// (0x1040 + 8) + (0 RoR 12) + (0 RoR 20) + (0xfc4) = 0x200c
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// (0x1040 + 8) + (0 RoR 12) + 4096 + (0xfc4) = 0x300c
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// DSO-NEXT: 1040: 00 c6 8f e2 add r12, pc, #0, #12
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// DSO-NEXT: 1044: 01 ca 8c e2 add r12, r12, #4096
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// DSO-NEXT: 1048: c4 ff bc e5 ldr pc, [r12, #4036]!
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// DSO: $d:
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// DSO-NEXT: 104c: d4 d4 d4 d4 .word 0xd4d4d4d4
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// DSO: $a:
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// (0x1050 + 8) + (0 RoR 12) + (0 RoR 20) + (0xfb8) = 0x2010
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// (0x1050 + 8) + (0 RoR 12) + 4096 + (0xfb8) = 0x3010
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// DSO-NEXT: 1050: 00 c6 8f e2 add r12, pc, #0, #12
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// DSO-NEXT: 1054: 01 ca 8c e2 add r12, r12, #4096
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// DSO-NEXT: 1058: b8 ff bc e5 ldr pc, [r12, #4024]!
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// DSO: $d:
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// DSO-NEXT: 105c: d4 d4 d4 d4 .word 0xd4d4d4d4
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// DSO: $a:
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// (0x1060 + 8) + (0 RoR 12) + (0 RoR 20) + (0xfac) = 0x2014
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// (0x1060 + 8) + (0 RoR 12) + 4096 + (0xfac) = 0x3014
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// DSO-NEXT: 1060: 00 c6 8f e2 add r12, pc, #0, #12
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// DSO-NEXT: 1064: 01 ca 8c e2 add r12, r12, #4096
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// DSO-NEXT: 1068: ac ff bc e5 ldr pc, [r12, #4012]!
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@ -60,7 +60,7 @@ _start:
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// DSOARM: Disassembly of section .plt:
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// DSOARM-NEXT: $a:
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// DSOARM-NEXT: 1020: 04 e0 2d e5 str lr, [sp, #-4]!
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// (0x1024 + 8) + (0 RoR 12) + (0 RoR 20) + (0xfdc) = 0x2008 = .got.plt[3]
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// (0x1024 + 8) + (0 RoR 12) + 4096 + (0xfdc) = 0x3008 = .got.plt[3]
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// DSOARM-NEXT: 1024: 00 e6 8f e2 add lr, pc, #0, #12
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// DSOARM-NEXT: 1028: 01 ea 8e e2 add lr, lr, #4096
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// DSOARM-NEXT: 102c: dc ff be e5 ldr pc, [lr, #4060]!
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@ -71,21 +71,21 @@ _start:
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// DSOARM-NEXT: 1038: d4 d4 d4 d4 .word 0xd4d4d4d4
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// DSOARM-NEXT: 103c: d4 d4 d4 d4 .word 0xd4d4d4d4
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// DSOARM: $a:
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// (0x1040 + 8) + (0 RoR 12) + (0 RoR 20) + (0xfc4) = 0x200c
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// (0x1040 + 8) + (0 RoR 12) + 4096 + (0xfc4) = 0x300c
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// DSOARM-NEXT: 1040: 00 c6 8f e2 add r12, pc, #0, #12
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// DSOARM-NEXT: 1044: 01 ca 8c e2 add r12, r12, #4096
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// DSOARM-NEXT: 1048: c4 ff bc e5 ldr pc, [r12, #4036]!
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// DSOARM: $d:
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// DSOARM-NEXT: 104c: d4 d4 d4 d4 .word 0xd4d4d4d4
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// DSOARM: $a:
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// (0x1050 + 8) + (0 RoR 12) + (0 RoR 20) + (0xfb8) = 0x2010
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// (0x1050 + 8) + (0 RoR 12) + 4096 + (0xfb8) = 0x3010
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// DSOARM-NEXT: 1050: 00 c6 8f e2 add r12, pc, #0, #12
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// DSOARM-NEXT: 1054: 01 ca 8c e2 add r12, r12, #4096
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// DSOARM-NEXT: 1058: b8 ff bc e5 ldr pc, [r12, #4024]!
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// DSOARM: $d:
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// DSOARM-NEXT: 105c: d4 d4 d4 d4 .word 0xd4d4d4d4
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// DSOARM: $a:
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// (0x1060 + 8) + (0 RoR 12) + (0 RoR 20) + (0xfac) = 0x2014
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// (0x1060 + 8) + (0 RoR 12) + 4096 + (0xfac) = 0x3014
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// DSOARM-NEXT: 1060: 00 c6 8f e2 add r12, pc, #0, #12
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// DSOARM-NEXT: 1064: 01 ca 8c e2 add r12, r12, #4096
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// DSOARM-NEXT: 1068: ac ff bc e5 ldr pc, [r12, #4012]!
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@ -1,7 +1,7 @@
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// REQUIRES: arm, aarch64
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// RUN: llvm-mc -filetype=obj -triple=aarch64-none-linux-android %s -o %t.o
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// RUN: ld.lld -shared %t.o -o %t.so --pack-dyn-relocs=android
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// RUN: ld.lld -shared %t.o -o %t.so --pack-dyn-relocs=android -z norelro
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// RUN: llvm-readobj -s %t.so | FileCheck %s
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// This test is making sure the Android packed relocation support doesn't
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@ -16,36 +16,36 @@
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// CHECK-NEXT: Flags [ (0x2)
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// CHECK-NEXT: SHF_ALLOC (0x2)
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// CHECK-NEXT: ]
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// CHECK-NEXT: Address: 0x248
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// CHECK-NEXT: Offset: 0x248
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// CHECK-NEXT: Size: 22
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// CHECK-NEXT: Address: 0x1D8
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// CHECK-NEXT: Offset: 0x1D8
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// CHECK-NEXT: Size: 21
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// CHECK: Name: x (43)
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// CHECK-NEXT: Type: SHT_PROGBITS (0x1)
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// CHECK-NEXT: Flags [ (0x2)
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// CHECK-NEXT: SHF_ALLOC (0x2)
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// CHECK-NEXT: ]
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// CHECK-NEXT: Address: 0x25E
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// CHECK-NEXT: Offset: 0x25E
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// CHECK-NEXT: Size: 64980
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// CHECK-NEXT: Address: 0x1ED
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// CHECK-NEXT: Offset: 0x1ED
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// CHECK-NEXT: Size: 65036
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// CHECK: Name: barr (45)
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// CHECK-NEXT: Type: SHT_PROGBITS (0x1)
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// CHECK-NEXT: Flags [ (0x2)
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// CHECK-NEXT: SHF_ALLOC (0x2)
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// CHECK-NEXT: ]
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// CHECK-NEXT: Address: 0x10032
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// CHECK-NEXT: Offset: 0x10032
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// CHECK-NEXT: Address: 0xFFFA
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// CHECK-NEXT: Offset: 0xFFFA
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// CHECK-NEXT: Size: 0
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// CHECK: Name: foo (71)
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// CHECK: Name: foo (62)
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// CHECK-NEXT: Type: SHT_PROGBITS (0x1)
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// CHECK-NEXT: Flags [ (0x3)
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// CHECK-NEXT: SHF_ALLOC (0x2)
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// CHECK-NEXT: SHF_WRITE (0x1)
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// CHECK-NEXT: ]
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// CHECK-NEXT: Address: 0x30004
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// CHECK-NEXT: Offset: 0x30004
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// CHECK-NEXT: Address: 0x10004
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// CHECK-NEXT: Offset: 0x10004
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// CHECK-NEXT: Size: 12
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@ -59,7 +59,7 @@ foof:
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.long bar
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.section x,"a"
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.zero 64980
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.zero 65036
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.section barr,"a"
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.p2align 1
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