forked from OSchip/llvm-project
[VE] Implement JumpTable
Implement JumpTable to make BRIND work on VE. Update an existing br_jt regression test also. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D91582
This commit is contained in:
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c4472f8b4c
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f4517bbd73
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@ -92,8 +92,8 @@ void VEFrameLowering::emitEpilogueInsns(MachineFunction &MF,
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//
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//
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// or %sp, 0, %fp
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// or %sp, 0, %fp
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// ld %s17, 40(,%sp) iff this function is using s17 as BP
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// ld %s17, 40(,%sp) iff this function is using s17 as BP
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// ld %got, 32(,%sp)
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// ld %plt, 32(,%sp)
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// ld %plt, 24(,%sp)
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// ld %got, 24(,%sp)
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// ld %lr, 8(,%sp)
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// ld %lr, 8(,%sp)
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// ld %fp, 0(,%sp)
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// ld %fp, 0(,%sp)
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BuildMI(MBB, MBBI, DL, TII.get(VE::ORri), VE::SX11).addReg(VE::SX9).addImm(0);
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BuildMI(MBB, MBBI, DL, TII.get(VE::ORri), VE::SX11).addReg(VE::SX9).addImm(0);
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@ -21,6 +21,7 @@
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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@ -153,6 +154,7 @@ void VETargetLowering::initSPUActions() {
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setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
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setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
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setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
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setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
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setOperationAction(ISD::ConstantPool, PtrVT, Custom);
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setOperationAction(ISD::ConstantPool, PtrVT, Custom);
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setOperationAction(ISD::JumpTable, PtrVT, Custom);
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/// VAARG handling {
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/// VAARG handling {
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setOperationAction(ISD::VASTART, MVT::Other, Custom);
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setOperationAction(ISD::VASTART, MVT::Other, Custom);
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@ -173,9 +175,7 @@ void VETargetLowering::initSPUActions() {
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// VE doesn't have BRCOND
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// VE doesn't have BRCOND
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setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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// BRIND and BR_JT are not implemented yet.
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// BR_JT is not implemented yet.
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// FIXME: Implement both for the scalar perforamnce.
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setOperationAction(ISD::BRIND, MVT::Other, Expand);
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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/// } Branch
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/// } Branch
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@ -929,6 +929,9 @@ SDValue VETargetLowering::withTargetFlags(SDValue Op, unsigned TF,
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return DAG.getTargetExternalSymbol(ES->getSymbol(), ES->getValueType(0),
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return DAG.getTargetExternalSymbol(ES->getSymbol(), ES->getValueType(0),
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TF);
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TF);
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if (const JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op))
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return DAG.getTargetJumpTable(JT->getIndex(), JT->getValueType(0), TF);
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llvm_unreachable("Unhandled address SDNode");
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llvm_unreachable("Unhandled address SDNode");
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}
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}
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@ -957,7 +960,7 @@ SDValue VETargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
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MFI.setHasCalls(true);
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MFI.setHasCalls(true);
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auto GlobalN = dyn_cast<GlobalAddressSDNode>(Op);
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auto GlobalN = dyn_cast<GlobalAddressSDNode>(Op);
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if (isa<ConstantPoolSDNode>(Op) ||
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if (isa<ConstantPoolSDNode>(Op) || isa<JumpTableSDNode>(Op) ||
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(GlobalN && GlobalN->getGlobal()->hasLocalLinkage())) {
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(GlobalN && GlobalN->getGlobal()->hasLocalLinkage())) {
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// Create following instructions for local linkage PIC code.
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// Create following instructions for local linkage PIC code.
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// lea %reg, label@gotoff_lo
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// lea %reg, label@gotoff_lo
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@ -1147,6 +1150,10 @@ SDValue VETargetLowering::lowerGlobalTLSAddress(SDValue Op,
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return lowerToTLSGeneralDynamicModel(Op, DAG);
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return lowerToTLSGeneralDynamicModel(Op, DAG);
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}
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}
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SDValue VETargetLowering::lowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
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return makeAddress(Op, DAG);
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}
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// Lower a f128 load into two f64 loads.
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// Lower a f128 load into two f64 loads.
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static SDValue lowerLoadF128(SDValue Op, SelectionDAG &DAG) {
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static SDValue lowerLoadF128(SDValue Op, SelectionDAG &DAG) {
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SDLoc DL(Op);
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SDLoc DL(Op);
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@ -1412,6 +1419,8 @@ SDValue VETargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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return lowerGlobalAddress(Op, DAG);
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return lowerGlobalAddress(Op, DAG);
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case ISD::GlobalTLSAddress:
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case ISD::GlobalTLSAddress:
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return lowerGlobalTLSAddress(Op, DAG);
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return lowerGlobalTLSAddress(Op, DAG);
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case ISD::JumpTable:
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return lowerJumpTable(Op, DAG);
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case ISD::LOAD:
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case ISD::LOAD:
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return lowerLOAD(Op, DAG);
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return lowerLOAD(Op, DAG);
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case ISD::STORE:
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case ISD::STORE:
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@ -1424,6 +1433,63 @@ SDValue VETargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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}
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}
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/// } Custom Lower
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/// } Custom Lower
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/// JumpTable for VE.
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///
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/// VE cannot generate relocatable symbol in jump table. VE cannot
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/// generate expressions using symbols in both text segment and data
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/// segment like below.
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/// .4byte .LBB0_2-.LJTI0_0
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/// So, we generate offset from the top of function like below as
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/// a custom label.
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/// .4byte .LBB0_2-<function name>
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unsigned VETargetLowering::getJumpTableEncoding() const {
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// Use custom label for PIC.
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if (isPositionIndependent())
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return MachineJumpTableInfo::EK_Custom32;
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// Otherwise, use the normal jump table encoding heuristics.
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return TargetLowering::getJumpTableEncoding();
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}
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const MCExpr *VETargetLowering::LowerCustomJumpTableEntry(
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const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB,
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unsigned Uid, MCContext &Ctx) const {
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assert(isPositionIndependent());
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// Generate custom label for PIC like below.
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// .4bytes .LBB0_2-<function name>
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const auto *Value = MCSymbolRefExpr::create(MBB->getSymbol(), Ctx);
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MCSymbol *Sym = Ctx.getOrCreateSymbol(MBB->getParent()->getName().data());
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const auto *Base = MCSymbolRefExpr::create(Sym, Ctx);
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return MCBinaryExpr::createSub(Value, Base, Ctx);
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}
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SDValue VETargetLowering::getPICJumpTableRelocBase(SDValue Table,
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SelectionDAG &DAG) const {
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assert(isPositionIndependent());
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SDLoc DL(Table);
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Function *Function = &DAG.getMachineFunction().getFunction();
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assert(Function != nullptr);
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auto PtrTy = getPointerTy(DAG.getDataLayout(), Function->getAddressSpace());
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// In the jump table, we have following values in PIC mode.
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// .4bytes .LBB0_2-<function name>
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// We need to add this value and the address of this function to generate
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// .LBB0_2 label correctly under PIC mode. So, we want to generate following
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// instructions:
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// lea %reg, fun@gotoff_lo
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// and %reg, %reg, (32)0
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// lea.sl %reg, fun@gotoff_hi(%reg, %got)
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// In order to do so, we need to genarate correctly marked DAG node using
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// makeHiLoPair.
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SDValue Op = DAG.getGlobalAddress(Function, DL, PtrTy);
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SDValue HiLo = makeHiLoPair(Op, VEMCExpr::VK_VE_GOTOFF_HI32,
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VEMCExpr::VK_VE_GOTOFF_LO32, DAG);
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SDValue GlobalBase = DAG.getNode(VEISD::GLOBAL_BASE_REG, DL, PtrTy);
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return DAG.getNode(ISD::ADD, DL, PtrTy, GlobalBase, HiLo);
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}
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static bool isI32Insn(const SDNode *User, const SDNode *N) {
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static bool isI32Insn(const SDNode *User, const SDNode *N) {
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switch (User->getOpcode()) {
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switch (User->getOpcode()) {
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default:
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default:
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@ -92,6 +92,15 @@ public:
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/// Custom Lower {
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/// Custom Lower {
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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unsigned getJumpTableEncoding() const override;
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const MCExpr *LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
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const MachineBasicBlock *MBB,
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unsigned Uid,
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MCContext &Ctx) const override;
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SDValue getPICJumpTableRelocBase(SDValue Table,
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SelectionDAG &DAG) const override;
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// VE doesn't need getPICJumpTableRelocBaseExpr since it is used for only
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// EK_LabelDifference32.
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SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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@ -99,6 +108,7 @@ public:
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SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerToTLSGeneralDynamicModel(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerToTLSGeneralDynamicModel(SDValue Op, SelectionDAG &DAG) const;
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@ -1603,7 +1603,7 @@ def vehi_lo : OutPatFrag<(ops node:$hi, node:$lo),
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def vehi_baselo : OutPatFrag<(ops node:$base, node:$hi, node:$lo),
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def vehi_baselo : OutPatFrag<(ops node:$base, node:$hi, node:$lo),
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(LEASLrri $base, $lo, $hi)>;
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(LEASLrri $base, $lo, $hi)>;
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foreach type = [ "tblockaddress", "tconstpool", "texternalsym", "tglobaladdr",
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foreach type = [ "tblockaddress", "tconstpool", "texternalsym", "tglobaladdr",
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"tglobaltlsaddr" ] in {
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"tglobaltlsaddr", "tjumptable" ] in {
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def : Pat<(VElo !cast<SDNode>(type):$lo), (velo_only $lo)>;
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def : Pat<(VElo !cast<SDNode>(type):$lo), (velo_only $lo)>;
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def : Pat<(VEhi !cast<SDNode>(type):$hi), (vehi_only $hi)>;
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def : Pat<(VEhi !cast<SDNode>(type):$hi), (vehi_only $hi)>;
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def : Pat<(add (VEhi !cast<SDNode>(type):$hi), I64:$lo), (vehi_lo $hi, $lo)>;
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def : Pat<(add (VEhi !cast<SDNode>(type):$hi), I64:$lo), (vehi_lo $hi, $lo)>;
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@ -63,7 +63,8 @@ static MCOperand LowerOperand(const MachineInstr *MI, const MachineOperand &MO,
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return LowerSymbolOperand(MI, MO, AP.getSymbol(MO.getGlobal()), AP);
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return LowerSymbolOperand(MI, MO, AP.getSymbol(MO.getGlobal()), AP);
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case MachineOperand::MO_Immediate:
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case MachineOperand::MO_Immediate:
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return MCOperand::createImm(MO.getImm());
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return MCOperand::createImm(MO.getImm());
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case MachineOperand::MO_JumpTableIndex:
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return LowerSymbolOperand(MI, MO, AP.GetJTISymbol(MO.getIndex()), AP);
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case MachineOperand::MO_MachineBasicBlock:
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case MachineOperand::MO_MachineBasicBlock:
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return LowerSymbolOperand(MI, MO, MO.getMBB()->getSymbol(), AP);
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return LowerSymbolOperand(MI, MO, MO.getMBB()->getSymbol(), AP);
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@ -1,36 +1,96 @@
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; RUN: llc < %s -mtriple=ve | FileCheck %s
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; RUN: llc < %s -mtriple=ve | FileCheck %s
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; RUN: llc < %s -mtriple=ve -relocation-model=pic \
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; RUN: | FileCheck %s -check-prefix=PIC
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; Function Attrs: norecurse nounwind readnone
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @br_jt(i32 signext %0) {
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define signext i32 @br_jt(i32 signext %0) {
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; CHECK-LABEL: br_jt:
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; CHECK-LABEL: br_jt:
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; CHECK: # %bb.0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: brlt.w 2, %s0, .LBB{{[0-9]+}}_4
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; CHECK-NEXT: adds.w.sx %s1, -1, %s0
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; CHECK-NEXT: cmpu.w %s2, 3, %s1
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; CHECK-NEXT: brgt.w 0, %s2, .LBB{{[0-9]+}}_5
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: breq.w 1, %s0, .LBB{{[0-9]+}}_8
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: # %bb.2:
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; CHECK-NEXT: sll %s0, %s0, 3
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; CHECK-NEXT: brne.w 2, %s0, .LBB{{[0-9]+}}_7
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; CHECK-NEXT: lea %s1, .LJTI0_0@lo
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; CHECK-NEXT: # %bb.3:
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: lea.sl %s1, .LJTI0_0@hi(, %s1)
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; CHECK-NEXT: ld %s1, (%s1, %s0)
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; CHECK-NEXT: or %s0, 3, (0)1
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; CHECK-NEXT: b.l.t (, %s1)
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; CHECK-NEXT: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s0, 0, (0)1
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; CHECK-NEXT: or %s0, 0, (0)1
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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; CHECK-NEXT: b.l.t (, %s10)
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; CHECK-NEXT: .LBB{{[0-9]+}}_4:
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; CHECK-NEXT: .LBB{{[0-9]+}}_3:
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; CHECK-NEXT: breq.w 3, %s0, .LBB{{[0-9]+}}_9
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; CHECK-NEXT: # %bb.5:
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; CHECK-NEXT: brne.w 4, %s0, .LBB{{[0-9]+}}_7
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; CHECK-NEXT: # %bb.6:
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; CHECK-NEXT: or %s0, 7, (0)1
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; CHECK-NEXT: .LBB{{[0-9]+}}_7:
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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; CHECK-NEXT: .LBB{{[0-9]+}}_8:
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; CHECK-NEXT: or %s0, 3, (0)1
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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; CHECK-NEXT: .LBB{{[0-9]+}}_9:
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; CHECK-NEXT: or %s0, 4, (0)1
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; CHECK-NEXT: or %s0, 4, (0)1
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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; CHECK-NEXT: b.l.t (, %s10)
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; CHECK-NEXT: .LBB{{[0-9]+}}_4:
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; CHECK-NEXT: or %s0, 7, (0)1
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; CHECK-NEXT: .LBB{{[0-9]+}}_5:
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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;
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; PIC-LABEL: br_jt:
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; PIC: # %bb.0:
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; PIC-NEXT: st %s9, (, %s11)
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; PIC-NEXT: st %s10, 8(, %s11)
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; PIC-NEXT: st %s15, 24(, %s11)
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; PIC-NEXT: st %s16, 32(, %s11)
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; PIC-NEXT: or %s9, 0, %s11
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; PIC-NEXT: lea %s13, -176
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; PIC-NEXT: and %s13, %s13, (32)0
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; PIC-NEXT: lea.sl %s11, -1(%s13, %s11)
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; PIC-NEXT: brge.l %s11, %s8, .LBB0_7
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; PIC-NEXT: # %bb.6:
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; PIC-NEXT: ld %s61, 24(, %s14)
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; PIC-NEXT: or %s62, 0, %s0
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; PIC-NEXT: lea %s63, 315
|
||||||
|
; PIC-NEXT: shm.l %s63, (%s61)
|
||||||
|
; PIC-NEXT: shm.l %s8, 8(%s61)
|
||||||
|
; PIC-NEXT: shm.l %s11, 16(%s61)
|
||||||
|
; PIC-NEXT: monc
|
||||||
|
; PIC-NEXT: or %s0, 0, %s62
|
||||||
|
; PIC-NEXT: .LBB0_7:
|
||||||
|
; PIC-NEXT: adds.w.sx %s0, %s0, (0)1
|
||||||
|
; PIC-NEXT: adds.w.sx %s1, -1, %s0
|
||||||
|
; PIC-NEXT: cmpu.w %s2, 3, %s1
|
||||||
|
; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
|
||||||
|
; PIC-NEXT: and %s15, %s15, (32)0
|
||||||
|
; PIC-NEXT: sic %s16
|
||||||
|
; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15)
|
||||||
|
; PIC-NEXT: brgt.w 0, %s2, .LBB0_5
|
||||||
|
; PIC-NEXT: # %bb.1:
|
||||||
|
; PIC-NEXT: adds.w.zx %s0, %s1, (0)1
|
||||||
|
; PIC-NEXT: sll %s0, %s0, 2
|
||||||
|
; PIC-NEXT: lea %s1, .LJTI0_0@gotoff_lo
|
||||||
|
; PIC-NEXT: and %s1, %s1, (32)0
|
||||||
|
; PIC-NEXT: lea.sl %s1, .LJTI0_0@gotoff_hi(%s1, %s15)
|
||||||
|
; PIC-NEXT: ldl.sx %s0, (%s1, %s0)
|
||||||
|
; PIC-NEXT: lea %s1, br_jt@gotoff_lo
|
||||||
|
; PIC-NEXT: and %s1, %s1, (32)0
|
||||||
|
; PIC-NEXT: lea.sl %s1, br_jt@gotoff_hi(%s1, %s15)
|
||||||
|
; PIC-NEXT: adds.l %s1, %s0, %s1
|
||||||
|
; PIC-NEXT: or %s0, 3, (0)1
|
||||||
|
; PIC-NEXT: b.l.t (, %s1)
|
||||||
|
; PIC-NEXT: .LBB0_2:
|
||||||
|
; PIC-NEXT: or %s0, 0, (0)1
|
||||||
|
; PIC-NEXT: br.l.t .LBB0_5
|
||||||
|
; PIC-NEXT: .LBB0_3:
|
||||||
|
; PIC-NEXT: or %s0, 4, (0)1
|
||||||
|
; PIC-NEXT: br.l.t .LBB0_5
|
||||||
|
; PIC-NEXT: .LBB0_4:
|
||||||
|
; PIC-NEXT: or %s0, 7, (0)1
|
||||||
|
; PIC-NEXT: .LBB0_5:
|
||||||
|
; PIC-NEXT: adds.w.sx %s0, %s0, (0)1
|
||||||
|
; PIC-NEXT: or %s11, 0, %s9
|
||||||
|
; PIC-NEXT: ld %s16, 32(, %s11)
|
||||||
|
; PIC-NEXT: ld %s15, 24(, %s11)
|
||||||
|
; PIC-NEXT: ld %s10, 8(, %s11)
|
||||||
|
; PIC-NEXT: ld %s9, (, %s11)
|
||||||
|
; PIC-NEXT: b.l.t (, %s10)
|
||||||
switch i32 %0, label %5 [
|
switch i32 %0, label %5 [
|
||||||
i32 1, label %6
|
i32 1, label %6
|
||||||
i32 2, label %2
|
i32 2, label %2
|
||||||
|
|
Loading…
Reference in New Issue