forked from OSchip/llvm-project
[ARM] A couple of extra VMOVimm tests, useful for showing BE codegen. NFC
This commit is contained in:
David Green
parent
c0edcec630
commit
f44770c329
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@ -21,6 +21,37 @@ entry:
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ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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}
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define arm_aapcs_vfpcc <16 x i8> @mov_int8_1234() {
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; CHECKLE-LABEL: mov_int8_1234:
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; CHECKLE: @ %bb.0: @ %entry
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; CHECKLE-NEXT: adr r0, .LCPI2_0
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; CHECKLE-NEXT: vldrw.u32 q0, [r0]
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; CHECKLE-NEXT: bx lr
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; CHECKLE-NEXT: .p2align 4
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; CHECKLE-NEXT: @ %bb.1:
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; CHECKLE-NEXT: .LCPI2_0:
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; CHECKLE-NEXT: .long 67305985 @ double 2.4380727978175888E-289
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; CHECKLE-NEXT: .long 67305985
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; CHECKLE-NEXT: .long 67305985 @ double 2.4380727978175888E-289
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; CHECKLE-NEXT: .long 67305985
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;
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; CHECKBE-LABEL: mov_int8_1234:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: adr r0, .LCPI2_0
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; CHECKBE-NEXT: vldrb.u8 q1, [r0]
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; CHECKBE-NEXT: vrev64.8 q0, q1
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; CHECKBE-NEXT: bx lr
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; CHECKBE-NEXT: .p2align 4
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; CHECKBE-NEXT: @ %bb.1:
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; CHECKBE-NEXT: .LCPI2_0:
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; CHECKBE-NEXT: .long 16909060 @ double 8.2078802900595913E-304
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; CHECKBE-NEXT: .long 16909060
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; CHECKBE-NEXT: .long 16909060 @ double 8.2078802900595913E-304
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; CHECKBE-NEXT: .long 16909060
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entry:
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ret <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4>
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}
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define arm_aapcs_vfpcc <8 x i16> @mov_int16_1() {
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; CHECK-LABEL: mov_int16_1:
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; CHECK: @ %bb.0: @ %entry
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@ -60,12 +91,12 @@ entry:
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define arm_aapcs_vfpcc <8 x i16> @mov_int16_258() {
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; CHECKLE-LABEL: mov_int16_258:
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; CHECKLE: @ %bb.0: @ %entry
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; CHECKLE-NEXT: adr r0, .LCPI6_0
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; CHECKLE-NEXT: adr r0, .LCPI7_0
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; CHECKLE-NEXT: vldrw.u32 q0, [r0]
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; CHECKLE-NEXT: bx lr
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; CHECKLE-NEXT: .p2align 4
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; CHECKLE-NEXT: @ %bb.1:
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; CHECKLE-NEXT: .LCPI6_0:
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; CHECKLE-NEXT: .LCPI7_0:
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; CHECKLE-NEXT: .long 16908546 @ double 8.204306265173532E-304
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; CHECKLE-NEXT: .long 16908546
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; CHECKLE-NEXT: .long 16908546 @ double 8.204306265173532E-304
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@ -73,13 +104,13 @@ define arm_aapcs_vfpcc <8 x i16> @mov_int16_258() {
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;
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; CHECKBE-LABEL: mov_int16_258:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: adr r0, .LCPI6_0
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; CHECKBE-NEXT: adr r0, .LCPI7_0
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; CHECKBE-NEXT: vldrb.u8 q1, [r0]
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; CHECKBE-NEXT: vrev64.8 q0, q1
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; CHECKBE-NEXT: bx lr
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; CHECKBE-NEXT: .p2align 4
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; CHECKBE-NEXT: @ %bb.1:
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; CHECKBE-NEXT: .LCPI6_0:
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; CHECKBE-NEXT: .LCPI7_0:
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; CHECKBE-NEXT: .long 16908546 @ double 8.204306265173532E-304
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; CHECKBE-NEXT: .long 16908546
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; CHECKBE-NEXT: .long 16908546 @ double 8.204306265173532E-304
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@ -127,12 +158,12 @@ entry:
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define arm_aapcs_vfpcc <4 x i32> @mov_int32_16777217() {
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; CHECKLE-LABEL: mov_int32_16777217:
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; CHECKLE: @ %bb.0: @ %entry
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; CHECKLE-NEXT: adr r0, .LCPI11_0
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; CHECKLE-NEXT: adr r0, .LCPI12_0
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; CHECKLE-NEXT: vldrw.u32 q0, [r0]
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; CHECKLE-NEXT: bx lr
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; CHECKLE-NEXT: .p2align 4
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; CHECKLE-NEXT: @ %bb.1:
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; CHECKLE-NEXT: .LCPI11_0:
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; CHECKLE-NEXT: .LCPI12_0:
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; CHECKLE-NEXT: .long 16777217 @ double 7.2911290000737531E-304
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; CHECKLE-NEXT: .long 16777217
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; CHECKLE-NEXT: .long 16777217 @ double 7.2911290000737531E-304
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@ -140,13 +171,13 @@ define arm_aapcs_vfpcc <4 x i32> @mov_int32_16777217() {
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;
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; CHECKBE-LABEL: mov_int32_16777217:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: adr r0, .LCPI11_0
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; CHECKBE-NEXT: adr r0, .LCPI12_0
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; CHECKBE-NEXT: vldrb.u8 q1, [r0]
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; CHECKBE-NEXT: vrev64.8 q0, q1
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; CHECKBE-NEXT: bx lr
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; CHECKBE-NEXT: .p2align 4
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; CHECKBE-NEXT: @ %bb.1:
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; CHECKBE-NEXT: .LCPI11_0:
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; CHECKBE-NEXT: .LCPI12_0:
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; CHECKBE-NEXT: .long 16777217 @ double 7.2911290000737531E-304
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; CHECKBE-NEXT: .long 16777217
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; CHECKBE-NEXT: .long 16777217 @ double 7.2911290000737531E-304
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@ -194,12 +225,12 @@ entry:
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define arm_aapcs_vfpcc <4 x i32> @mov_int32_4278190335() {
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; CHECKLE-LABEL: mov_int32_4278190335:
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; CHECKLE: @ %bb.0: @ %entry
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; CHECKLE-NEXT: adr r0, .LCPI16_0
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; CHECKLE-NEXT: adr r0, .LCPI17_0
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; CHECKLE-NEXT: vldrw.u32 q0, [r0]
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; CHECKLE-NEXT: bx lr
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; CHECKLE-NEXT: .p2align 4
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; CHECKLE-NEXT: @ %bb.1:
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; CHECKLE-NEXT: .LCPI16_0:
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; CHECKLE-NEXT: .LCPI17_0:
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; CHECKLE-NEXT: .long 4278190335 @ double -5.4874634341155774E+303
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; CHECKLE-NEXT: .long 4278190335
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; CHECKLE-NEXT: .long 4278190335 @ double -5.4874634341155774E+303
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@ -207,13 +238,13 @@ define arm_aapcs_vfpcc <4 x i32> @mov_int32_4278190335() {
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;
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; CHECKBE-LABEL: mov_int32_4278190335:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: adr r0, .LCPI16_0
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; CHECKBE-NEXT: adr r0, .LCPI17_0
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; CHECKBE-NEXT: vldrb.u8 q1, [r0]
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; CHECKBE-NEXT: vrev64.8 q0, q1
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; CHECKBE-NEXT: bx lr
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; CHECKBE-NEXT: .p2align 4
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; CHECKBE-NEXT: @ %bb.1:
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; CHECKBE-NEXT: .LCPI16_0:
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; CHECKBE-NEXT: .LCPI17_0:
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; CHECKBE-NEXT: .long 4278190335 @ double -5.4874634341155774E+303
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; CHECKBE-NEXT: .long 4278190335
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; CHECKBE-NEXT: .long 4278190335 @ double -5.4874634341155774E+303
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@ -231,15 +262,46 @@ entry:
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ret <4 x i32> <i32 4278255615, i32 4278255615, i32 4278255615, i32 4278255615>
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}
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define arm_aapcs_vfpcc <2 x i64> @mov_int64_1() {
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; CHECKLE-LABEL: mov_int64_1:
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define arm_aapcs_vfpcc <4 x i32> @mov_int32_16908546() {
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; CHECKLE-LABEL: mov_int32_16908546:
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; CHECKLE: @ %bb.0: @ %entry
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; CHECKLE-NEXT: adr r0, .LCPI18_0
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; CHECKLE-NEXT: adr r0, .LCPI19_0
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; CHECKLE-NEXT: vldrw.u32 q0, [r0]
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; CHECKLE-NEXT: bx lr
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; CHECKLE-NEXT: .p2align 4
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; CHECKLE-NEXT: @ %bb.1:
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; CHECKLE-NEXT: .LCPI18_0:
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; CHECKLE-NEXT: .LCPI19_0:
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; CHECKLE-NEXT: .long 16908546 @ double 8.204306265173532E-304
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; CHECKLE-NEXT: .long 16908546
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; CHECKLE-NEXT: .long 16908546 @ double 8.204306265173532E-304
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; CHECKLE-NEXT: .long 16908546
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;
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; CHECKBE-LABEL: mov_int32_16908546:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: adr r0, .LCPI19_0
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; CHECKBE-NEXT: vldrb.u8 q1, [r0]
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; CHECKBE-NEXT: vrev64.8 q0, q1
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; CHECKBE-NEXT: bx lr
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; CHECKBE-NEXT: .p2align 4
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; CHECKBE-NEXT: @ %bb.1:
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; CHECKBE-NEXT: .LCPI19_0:
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; CHECKBE-NEXT: .long 16908546 @ double 8.204306265173532E-304
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; CHECKBE-NEXT: .long 16908546
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; CHECKBE-NEXT: .long 16908546 @ double 8.204306265173532E-304
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; CHECKBE-NEXT: .long 16908546
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entry:
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ret <4 x i32> <i32 16908546, i32 16908546, i32 16908546, i32 16908546>
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}
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define arm_aapcs_vfpcc <2 x i64> @mov_int64_1() {
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; CHECKLE-LABEL: mov_int64_1:
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; CHECKLE: @ %bb.0: @ %entry
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; CHECKLE-NEXT: adr r0, .LCPI20_0
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; CHECKLE-NEXT: vldrw.u32 q0, [r0]
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; CHECKLE-NEXT: bx lr
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; CHECKLE-NEXT: .p2align 4
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; CHECKLE-NEXT: @ %bb.1:
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; CHECKLE-NEXT: .LCPI20_0:
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; CHECKLE-NEXT: .long 1 @ double 4.9406564584124654E-324
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; CHECKLE-NEXT: .long 0
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; CHECKLE-NEXT: .long 1 @ double 4.9406564584124654E-324
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@ -247,13 +309,13 @@ define arm_aapcs_vfpcc <2 x i64> @mov_int64_1() {
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;
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; CHECKBE-LABEL: mov_int64_1:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: adr r0, .LCPI18_0
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; CHECKBE-NEXT: adr r0, .LCPI20_0
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; CHECKBE-NEXT: vldrb.u8 q1, [r0]
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; CHECKBE-NEXT: vrev64.8 q0, q1
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; CHECKBE-NEXT: bx lr
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; CHECKBE-NEXT: .p2align 4
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; CHECKBE-NEXT: @ %bb.1:
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; CHECKBE-NEXT: .LCPI18_0:
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; CHECKBE-NEXT: .LCPI20_0:
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; CHECKBE-NEXT: .long 0 @ double 4.9406564584124654E-324
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; CHECKBE-NEXT: .long 1
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; CHECKBE-NEXT: .long 0 @ double 4.9406564584124654E-324
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@ -292,12 +354,12 @@ entry:
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define arm_aapcs_vfpcc <2 x i64> @mov_int64_f_0() {
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; CHECKLE-LABEL: mov_int64_f_0:
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; CHECKLE: @ %bb.0: @ %entry
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; CHECKLE-NEXT: adr r0, .LCPI22_0
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; CHECKLE-NEXT: adr r0, .LCPI24_0
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; CHECKLE-NEXT: vldrw.u32 q0, [r0]
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; CHECKLE-NEXT: bx lr
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; CHECKLE-NEXT: .p2align 4
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; CHECKLE-NEXT: @ %bb.1:
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; CHECKLE-NEXT: .LCPI22_0:
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; CHECKLE-NEXT: .LCPI24_0:
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; CHECKLE-NEXT: .long 255 @ double 1.2598673968951787E-321
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; CHECKLE-NEXT: .long 0
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; CHECKLE-NEXT: .long 0 @ double 0
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@ -305,13 +367,13 @@ define arm_aapcs_vfpcc <2 x i64> @mov_int64_f_0() {
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;
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; CHECKBE-LABEL: mov_int64_f_0:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: adr r0, .LCPI22_0
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; CHECKBE-NEXT: adr r0, .LCPI24_0
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; CHECKBE-NEXT: vldrb.u8 q1, [r0]
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; CHECKBE-NEXT: vrev64.8 q0, q1
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; CHECKBE-NEXT: bx lr
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; CHECKBE-NEXT: .p2align 4
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; CHECKBE-NEXT: @ %bb.1:
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; CHECKBE-NEXT: .LCPI22_0:
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; CHECKBE-NEXT: .LCPI24_0:
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; CHECKBE-NEXT: .long 0 @ double 1.2598673968951787E-321
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; CHECKBE-NEXT: .long 255
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; CHECKBE-NEXT: .long 0 @ double 0
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@ -365,12 +427,12 @@ entry:
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define arm_aapcs_vfpcc <4 x float> @mov_float_1() {
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; CHECKLE-LABEL: mov_float_1:
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; CHECKLE: @ %bb.0: @ %entry
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; CHECKLE-NEXT: adr r0, .LCPI26_0
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; CHECKLE-NEXT: adr r0, .LCPI28_0
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; CHECKLE-NEXT: vldrw.u32 q0, [r0]
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; CHECKLE-NEXT: bx lr
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; CHECKLE-NEXT: .p2align 4
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; CHECKLE-NEXT: @ %bb.1:
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; CHECKLE-NEXT: .LCPI26_0:
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; CHECKLE-NEXT: .LCPI28_0:
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; CHECKLE-NEXT: .long 1065353216 @ double 0.007812501848093234
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; CHECKLE-NEXT: .long 1065353216
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; CHECKLE-NEXT: .long 1065353216 @ double 0.007812501848093234
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@ -378,13 +440,13 @@ define arm_aapcs_vfpcc <4 x float> @mov_float_1() {
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;
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; CHECKBE-LABEL: mov_float_1:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: adr r0, .LCPI26_0
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; CHECKBE-NEXT: adr r0, .LCPI28_0
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; CHECKBE-NEXT: vldrb.u8 q1, [r0]
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; CHECKBE-NEXT: vrev64.8 q0, q1
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; CHECKBE-NEXT: bx lr
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; CHECKBE-NEXT: .p2align 4
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; CHECKBE-NEXT: @ %bb.1:
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; CHECKBE-NEXT: .LCPI26_0:
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; CHECKBE-NEXT: .LCPI28_0:
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; CHECKBE-NEXT: .long 1065353216 @ double 0.007812501848093234
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; CHECKBE-NEXT: .long 1065353216
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; CHECKBE-NEXT: .long 1065353216 @ double 0.007812501848093234
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@ -396,12 +458,12 @@ entry:
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define arm_aapcs_vfpcc <4 x float> @mov_float_m3() {
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; CHECKLE-LABEL: mov_float_m3:
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; CHECKLE: @ %bb.0: @ %entry
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; CHECKLE-NEXT: adr r0, .LCPI27_0
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; CHECKLE-NEXT: adr r0, .LCPI29_0
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; CHECKLE-NEXT: vldrw.u32 q0, [r0]
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; CHECKLE-NEXT: bx lr
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; CHECKLE-NEXT: .p2align 4
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; CHECKLE-NEXT: @ %bb.1:
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; CHECKLE-NEXT: .LCPI27_0:
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; CHECKLE-NEXT: .LCPI29_0:
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; CHECKLE-NEXT: .long 3225419776 @ double -32.000022917985916
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; CHECKLE-NEXT: .long 3225419776
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; CHECKLE-NEXT: .long 3225419776 @ double -32.000022917985916
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@ -409,13 +471,13 @@ define arm_aapcs_vfpcc <4 x float> @mov_float_m3() {
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;
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; CHECKBE-LABEL: mov_float_m3:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: adr r0, .LCPI27_0
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; CHECKBE-NEXT: adr r0, .LCPI29_0
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; CHECKBE-NEXT: vldrb.u8 q1, [r0]
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; CHECKBE-NEXT: vrev64.8 q0, q1
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; CHECKBE-NEXT: bx lr
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; CHECKBE-NEXT: .p2align 4
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; CHECKBE-NEXT: @ %bb.1:
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; CHECKBE-NEXT: .LCPI27_0:
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; CHECKBE-NEXT: .LCPI29_0:
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; CHECKBE-NEXT: .long 3225419776 @ double -32.000022917985916
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; CHECKBE-NEXT: .long 3225419776
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; CHECKBE-NEXT: .long 3225419776 @ double -32.000022917985916
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@ -447,12 +509,12 @@ entry:
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define arm_aapcs_vfpcc <2 x double> @mov_double_1() {
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; CHECKLE-LABEL: mov_double_1:
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; CHECKLE: @ %bb.0: @ %entry
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; CHECKLE-NEXT: adr r0, .LCPI30_0
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; CHECKLE-NEXT: adr r0, .LCPI32_0
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; CHECKLE-NEXT: vldrw.u32 q0, [r0]
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; CHECKLE-NEXT: bx lr
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; CHECKLE-NEXT: .p2align 4
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; CHECKLE-NEXT: @ %bb.1:
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; CHECKLE-NEXT: .LCPI30_0:
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; CHECKLE-NEXT: .LCPI32_0:
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; CHECKLE-NEXT: .long 0 @ double 1
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; CHECKLE-NEXT: .long 1072693248
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; CHECKLE-NEXT: .long 0 @ double 1
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@ -460,13 +522,13 @@ define arm_aapcs_vfpcc <2 x double> @mov_double_1() {
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;
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; CHECKBE-LABEL: mov_double_1:
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; CHECKBE: @ %bb.0: @ %entry
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; CHECKBE-NEXT: adr r0, .LCPI30_0
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; CHECKBE-NEXT: adr r0, .LCPI32_0
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; CHECKBE-NEXT: vldrb.u8 q1, [r0]
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; CHECKBE-NEXT: vrev64.8 q0, q1
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; CHECKBE-NEXT: bx lr
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; CHECKBE-NEXT: .p2align 4
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; CHECKBE-NEXT: @ %bb.1:
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; CHECKBE-NEXT: .LCPI30_0:
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; CHECKBE-NEXT: .LCPI32_0:
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; CHECKBE-NEXT: .long 1072693248 @ double 1
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; CHECKBE-NEXT: .long 0
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; CHECKBE-NEXT: .long 1072693248 @ double 1
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