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[libunwind][ARM] Fix loading FP registers on big-endian targets 

Summary:
The function Unwind-EHABI.cpp:_Unwind_VRS_Pop loads the saved values of
64-bit FP registers as two 32-bit words because they might not be
8-byte aligned. Combining these words into a 64-bit value has to be
done differently on big-endian platforms.

Reviewers: ostannard, john.brawn, dmgreen

Reviewed By: ostannard

Subscribers: kristof.beyls, christof, libcxx-commits

Tags: #libc

Differential Revision: https://reviews.llvm.org/D64996

llvm-svn: 366587
This commit is contained in:
Mikhail Maltsev 2019-07-19 15:20:32 +00:00
parent fd8a3651f7
commit f41e627157
1 changed files with 7 additions and 2 deletions
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9
libunwind/src/Unwind-EHABI.cpp
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@ -941,8 +941,13 @@ _Unwind_VRS_Pop(_Unwind_Context *context, _Unwind_VRS_RegClass regclass,
// format 1", which is equivalent to FSTMD + a padding word.
for (uint32_t i = first; i < end; ++i) {
// SP is only 32-bit aligned so don't copy 64-bit at a time.
uint64_t value = *sp++;
value |= ((uint64_t)(*sp++)) << 32;
uint32_t w0 = *sp++;
uint32_t w1 = *sp++;
#ifdef __LITTLE_ENDIAN__
uint64_t value = (w1 << 32) | w0;
#else
uint64_t value = (w0 << 32) | w1;
#endif
if (_Unwind_VRS_Set(context, regclass, i, representation, &value) !=
_UVRSR_OK)
return _UVRSR_FAILED;