forked from OSchip/llvm-project
Use iPTR instead of i32 for extract_subvector/insert_subvector index in lowering and patterns. This makes it consistent with the incoming DAG nodes from the DAG builder.
llvm-svn: 163293
This commit is contained in:
Craig Topper
parent
daa5ed1e0a
commit
f3e4aa8cdd
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@ -85,7 +85,7 @@ static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
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unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
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* ElemsPerChunk);
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SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
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SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
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SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
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VecIdx);
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@ -118,7 +118,7 @@ static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
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unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
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* ElemsPerChunk);
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SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
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SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
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return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
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VecIdx);
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}
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@ -251,35 +251,35 @@ def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
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// A 128-bit subvector extract from the first 256-bit vector position
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// is a subregister copy that needs no instruction.
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def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
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def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
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(v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
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def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
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def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
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(v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
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def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
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def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
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(v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
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def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
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def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
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(v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
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def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
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def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
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(v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
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def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
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def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
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(v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
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// A 128-bit subvector insert to the first 256-bit vector position
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// is a subregister copy that needs no instruction.
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let AddedComplexity = 25 in { // to give priority over vinsertf128rm
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def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
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def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
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(INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
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def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
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def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
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(INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
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def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
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def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
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(INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
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def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
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def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
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(INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
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def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
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def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
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(INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
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def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
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def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
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(INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
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}
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@ -596,27 +596,27 @@ let Predicates = [HasAVX] in {
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// Represent the same patterns above but in the form they appear for
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// 256-bit types
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def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
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(v4i32 (scalar_to_vector (loadi32 addr:$src))), (i32 0)))),
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(v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
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(SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
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def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
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(v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
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(v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
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(SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
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def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
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(v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
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(v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
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(SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
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}
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def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
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(v4f32 (scalar_to_vector FR32:$src)), (i32 0)))),
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(v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
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(SUBREG_TO_REG (i32 0),
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(v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
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sub_xmm)>;
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def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
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(v2f64 (scalar_to_vector FR64:$src)), (i32 0)))),
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(v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
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(SUBREG_TO_REG (i64 0),
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(v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
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sub_xmm)>;
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def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
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(v2i64 (scalar_to_vector (loadi64 addr:$src))), (i32 0)))),
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(v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
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(SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
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// Move low f64 and clear high bits.
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@ -907,16 +907,16 @@ let isCodeGenOnly = 1 in {
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let Predicates = [HasAVX] in {
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def : Pat<(v8i32 (X86vzmovl
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(insert_subvector undef, (v4i32 VR128:$src), (i32 0)))),
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(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
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(SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
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def : Pat<(v4i64 (X86vzmovl
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(insert_subvector undef, (v2i64 VR128:$src), (i32 0)))),
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(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
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(SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
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def : Pat<(v8f32 (X86vzmovl
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(insert_subvector undef, (v4f32 VR128:$src), (i32 0)))),
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(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
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(SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
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def : Pat<(v4f64 (X86vzmovl
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(insert_subvector undef, (v2f64 VR128:$src), (i32 0)))),
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(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
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(SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
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}
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@ -1023,41 +1023,41 @@ let Predicates = [HasAVX] in {
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// Special patterns for storing subvector extracts of lower 128-bits
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// Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
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def : Pat<(alignedstore (v2f64 (extract_subvector
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(v4f64 VR256:$src), (i32 0))), addr:$dst),
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(v4f64 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(alignedstore (v4f32 (extract_subvector
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(v8f32 VR256:$src), (i32 0))), addr:$dst),
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(v8f32 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(alignedstore (v2i64 (extract_subvector
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(v4i64 VR256:$src), (i32 0))), addr:$dst),
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(v4i64 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(alignedstore (v4i32 (extract_subvector
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(v8i32 VR256:$src), (i32 0))), addr:$dst),
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(v8i32 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(alignedstore (v8i16 (extract_subvector
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(v16i16 VR256:$src), (i32 0))), addr:$dst),
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(v16i16 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(alignedstore (v16i8 (extract_subvector
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(v32i8 VR256:$src), (i32 0))), addr:$dst),
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(v32i8 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(store (v2f64 (extract_subvector
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(v4f64 VR256:$src), (i32 0))), addr:$dst),
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(v4f64 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(store (v4f32 (extract_subvector
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(v8f32 VR256:$src), (i32 0))), addr:$dst),
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(v8f32 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(store (v2i64 (extract_subvector
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(v4i64 VR256:$src), (i32 0))), addr:$dst),
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(v4i64 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(store (v4i32 (extract_subvector
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(v8i32 VR256:$src), (i32 0))), addr:$dst),
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(v8i32 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(store (v8i16 (extract_subvector
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(v16i16 VR256:$src), (i32 0))), addr:$dst),
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(v16i16 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(store (v16i8 (extract_subvector
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(v32i8 VR256:$src), (i32 0))), addr:$dst),
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(v32i8 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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}
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@ -4692,10 +4692,10 @@ let Predicates = [HasAVX] in {
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}
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// Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
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def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
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(v4i32 (scalar_to_vector GR32:$src)),(i32 0)))),
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(v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
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(SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
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def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
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(v2i64 (scalar_to_vector GR64:$src)),(i32 0)))),
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(v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
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(SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
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}
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@ -7255,59 +7255,59 @@ def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
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let Predicates = [HasAVX] in {
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def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
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(i32 imm)),
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(iPTR imm)),
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(VINSERTF128rr VR256:$src1, VR128:$src2,
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(INSERT_get_vinsertf128_imm VR256:$ins))>;
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def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
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(i32 imm)),
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(iPTR imm)),
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(VINSERTF128rr VR256:$src1, VR128:$src2,
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(INSERT_get_vinsertf128_imm VR256:$ins))>;
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def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (memopv4f32 addr:$src2),
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(i32 imm)),
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(iPTR imm)),
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(VINSERTF128rm VR256:$src1, addr:$src2,
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(INSERT_get_vinsertf128_imm VR256:$ins))>;
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def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (memopv2f64 addr:$src2),
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(i32 imm)),
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(iPTR imm)),
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(VINSERTF128rm VR256:$src1, addr:$src2,
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(INSERT_get_vinsertf128_imm VR256:$ins))>;
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}
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let Predicates = [HasAVX1Only] in {
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def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
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(i32 imm)),
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(iPTR imm)),
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(VINSERTF128rr VR256:$src1, VR128:$src2,
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(INSERT_get_vinsertf128_imm VR256:$ins))>;
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def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
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(i32 imm)),
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(iPTR imm)),
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(VINSERTF128rr VR256:$src1, VR128:$src2,
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(INSERT_get_vinsertf128_imm VR256:$ins))>;
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def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
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(i32 imm)),
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(iPTR imm)),
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(VINSERTF128rr VR256:$src1, VR128:$src2,
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(INSERT_get_vinsertf128_imm VR256:$ins))>;
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def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
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(i32 imm)),
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(iPTR imm)),
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(VINSERTF128rr VR256:$src1, VR128:$src2,
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(INSERT_get_vinsertf128_imm VR256:$ins))>;
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def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (memopv2i64 addr:$src2),
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(i32 imm)),
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(iPTR imm)),
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(VINSERTF128rm VR256:$src1, addr:$src2,
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(INSERT_get_vinsertf128_imm VR256:$ins))>;
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def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1),
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(bc_v4i32 (memopv2i64 addr:$src2)),
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(i32 imm)),
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(iPTR imm)),
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(VINSERTF128rm VR256:$src1, addr:$src2,
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(INSERT_get_vinsertf128_imm VR256:$ins))>;
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def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1),
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(bc_v16i8 (memopv2i64 addr:$src2)),
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(i32 imm)),
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(iPTR imm)),
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(VINSERTF128rm VR256:$src1, addr:$src2,
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(INSERT_get_vinsertf128_imm VR256:$ins))>;
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def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1),
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(bc_v8i16 (memopv2i64 addr:$src2)),
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(i32 imm)),
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(iPTR imm)),
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(VINSERTF128rm VR256:$src1, addr:$src2,
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(INSERT_get_vinsertf128_imm VR256:$ins))>;
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}
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@ -7329,57 +7329,57 @@ def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
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// AVX1 patterns
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let Predicates = [HasAVX] in {
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def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
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def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
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(v4f32 (VEXTRACTF128rr
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(v8f32 VR256:$src1),
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(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
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def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
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def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
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(v2f64 (VEXTRACTF128rr
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(v4f64 VR256:$src1),
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(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
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def : Pat<(alignedstore (v4f32 (vextractf128_extract:$ext (v8f32 VR256:$src1),
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(i32 imm))), addr:$dst),
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(iPTR imm))), addr:$dst),
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(VEXTRACTF128mr addr:$dst, VR256:$src1,
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(EXTRACT_get_vextractf128_imm VR128:$ext))>;
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def : Pat<(alignedstore (v2f64 (vextractf128_extract:$ext (v4f64 VR256:$src1),
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(i32 imm))), addr:$dst),
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(iPTR imm))), addr:$dst),
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(VEXTRACTF128mr addr:$dst, VR256:$src1,
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(EXTRACT_get_vextractf128_imm VR128:$ext))>;
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}
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let Predicates = [HasAVX1Only] in {
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def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
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def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
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(v2i64 (VEXTRACTF128rr
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(v4i64 VR256:$src1),
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(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
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def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
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def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
|
||||
(v4i32 (VEXTRACTF128rr
|
||||
(v8i32 VR256:$src1),
|
||||
(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
|
||||
def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
|
||||
def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
|
||||
(v8i16 (VEXTRACTF128rr
|
||||
(v16i16 VR256:$src1),
|
||||
(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
|
||||
def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
|
||||
def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
|
||||
(v16i8 (VEXTRACTF128rr
|
||||
(v32i8 VR256:$src1),
|
||||
(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
|
||||
|
||||
def : Pat<(alignedstore (v2i64 (vextractf128_extract:$ext (v4i64 VR256:$src1),
|
||||
(i32 imm))), addr:$dst),
|
||||
(iPTR imm))), addr:$dst),
|
||||
(VEXTRACTF128mr addr:$dst, VR256:$src1,
|
||||
(EXTRACT_get_vextractf128_imm VR128:$ext))>;
|
||||
def : Pat<(alignedstore (v4i32 (vextractf128_extract:$ext (v8i32 VR256:$src1),
|
||||
(i32 imm))), addr:$dst),
|
||||
(iPTR imm))), addr:$dst),
|
||||
(VEXTRACTF128mr addr:$dst, VR256:$src1,
|
||||
(EXTRACT_get_vextractf128_imm VR128:$ext))>;
|
||||
def : Pat<(alignedstore (v8i16 (vextractf128_extract:$ext (v16i16 VR256:$src1),
|
||||
(i32 imm))), addr:$dst),
|
||||
(iPTR imm))), addr:$dst),
|
||||
(VEXTRACTF128mr addr:$dst, VR256:$src1,
|
||||
(EXTRACT_get_vextractf128_imm VR128:$ext))>;
|
||||
def : Pat<(alignedstore (v16i8 (vextractf128_extract:$ext (v32i8 VR256:$src1),
|
||||
(i32 imm))), addr:$dst),
|
||||
(iPTR imm))), addr:$dst),
|
||||
(VEXTRACTF128mr addr:$dst, VR256:$src1,
|
||||
(EXTRACT_get_vextractf128_imm VR128:$ext))>;
|
||||
}
|
||||
|
|
@ -7850,39 +7850,39 @@ def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
|
|||
|
||||
let Predicates = [HasAVX2] in {
|
||||
def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
|
||||
(i32 imm)),
|
||||
(iPTR imm)),
|
||||
(VINSERTI128rr VR256:$src1, VR128:$src2,
|
||||
(INSERT_get_vinsertf128_imm VR256:$ins))>;
|
||||
def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
|
||||
(i32 imm)),
|
||||
(iPTR imm)),
|
||||
(VINSERTI128rr VR256:$src1, VR128:$src2,
|
||||
(INSERT_get_vinsertf128_imm VR256:$ins))>;
|
||||
def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
|
||||
(i32 imm)),
|
||||
(iPTR imm)),
|
||||
(VINSERTI128rr VR256:$src1, VR128:$src2,
|
||||
(INSERT_get_vinsertf128_imm VR256:$ins))>;
|
||||
def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
|
||||
(i32 imm)),
|
||||
(iPTR imm)),
|
||||
(VINSERTI128rr VR256:$src1, VR128:$src2,
|
||||
(INSERT_get_vinsertf128_imm VR256:$ins))>;
|
||||
|
||||
def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (memopv2i64 addr:$src2),
|
||||
(i32 imm)),
|
||||
(iPTR imm)),
|
||||
(VINSERTI128rm VR256:$src1, addr:$src2,
|
||||
(INSERT_get_vinsertf128_imm VR256:$ins))>;
|
||||
def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1),
|
||||
(bc_v4i32 (memopv2i64 addr:$src2)),
|
||||
(i32 imm)),
|
||||
(iPTR imm)),
|
||||
(VINSERTI128rm VR256:$src1, addr:$src2,
|
||||
(INSERT_get_vinsertf128_imm VR256:$ins))>;
|
||||
def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1),
|
||||
(bc_v16i8 (memopv2i64 addr:$src2)),
|
||||
(i32 imm)),
|
||||
(iPTR imm)),
|
||||
(VINSERTI128rm VR256:$src1, addr:$src2,
|
||||
(INSERT_get_vinsertf128_imm VR256:$ins))>;
|
||||
def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1),
|
||||
(bc_v8i16 (memopv2i64 addr:$src2)),
|
||||
(i32 imm)),
|
||||
(iPTR imm)),
|
||||
(VINSERTI128rm VR256:$src1, addr:$src2,
|
||||
(INSERT_get_vinsertf128_imm VR256:$ins))>;
|
||||
}
|
||||
|
|
@ -7902,37 +7902,37 @@ def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
|
|||
"vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, VEX;
|
||||
|
||||
let Predicates = [HasAVX2] in {
|
||||
def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
|
||||
def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
|
||||
(v2i64 (VEXTRACTI128rr
|
||||
(v4i64 VR256:$src1),
|
||||
(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
|
||||
def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
|
||||
def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
|
||||
(v4i32 (VEXTRACTI128rr
|
||||
(v8i32 VR256:$src1),
|
||||
(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
|
||||
def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
|
||||
def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
|
||||
(v8i16 (VEXTRACTI128rr
|
||||
(v16i16 VR256:$src1),
|
||||
(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
|
||||
def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
|
||||
def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
|
||||
(v16i8 (VEXTRACTI128rr
|
||||
(v32i8 VR256:$src1),
|
||||
(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
|
||||
|
||||
def : Pat<(alignedstore (v2i64 (vextractf128_extract:$ext (v4i64 VR256:$src1),
|
||||
(i32 imm))), addr:$dst),
|
||||
(iPTR imm))), addr:$dst),
|
||||
(VEXTRACTI128mr addr:$dst, VR256:$src1,
|
||||
(EXTRACT_get_vextractf128_imm VR128:$ext))>;
|
||||
def : Pat<(alignedstore (v4i32 (vextractf128_extract:$ext (v8i32 VR256:$src1),
|
||||
(i32 imm))), addr:$dst),
|
||||
(iPTR imm))), addr:$dst),
|
||||
(VEXTRACTI128mr addr:$dst, VR256:$src1,
|
||||
(EXTRACT_get_vextractf128_imm VR128:$ext))>;
|
||||
def : Pat<(alignedstore (v8i16 (vextractf128_extract:$ext (v16i16 VR256:$src1),
|
||||
(i32 imm))), addr:$dst),
|
||||
(iPTR imm))), addr:$dst),
|
||||
(VEXTRACTI128mr addr:$dst, VR256:$src1,
|
||||
(EXTRACT_get_vextractf128_imm VR128:$ext))>;
|
||||
def : Pat<(alignedstore (v16i8 (vextractf128_extract:$ext (v32i8 VR256:$src1),
|
||||
(i32 imm))), addr:$dst),
|
||||
(iPTR imm))), addr:$dst),
|
||||
(VEXTRACTI128mr addr:$dst, VR256:$src1,
|
||||
(EXTRACT_get_vextractf128_imm VR128:$ext))>;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue