forked from OSchip/llvm-project
Added for disassembly only the variants of DMB, DSB, and ISB.
llvm-svn: 96540
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@ -1868,6 +1868,7 @@ def Int_MemBarrierV7 : AInoP<(outs), (ins),
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Requires<[IsARM, HasV7]> {
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let Inst{31-4} = 0xf57ff05;
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// FIXME: add support for options other than a full system DMB
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// See DMB disassembly-only variants below.
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let Inst{3-0} = 0b1111;
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}
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@ -1878,6 +1879,7 @@ def Int_SyncBarrierV7 : AInoP<(outs), (ins),
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Requires<[IsARM, HasV7]> {
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let Inst{31-4} = 0xf57ff04;
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// FIXME: add support for options other than a full system DSB
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// See DSB disassembly-only variants below.
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let Inst{3-0} = 0b1111;
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}
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@ -1900,6 +1902,64 @@ def Int_SyncBarrierV6 : AInoP<(outs), (ins GPR:$zero),
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}
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}
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// Helper class for multiclass MemB -- for disassembly only
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class AMBI<string opc, string asm>
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: AInoP<(outs), (ins), MiscFrm, NoItinerary, opc, asm,
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[/* For disassembly only; pattern left blank */]>,
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Requires<[IsARM, HasV7]> {
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let Inst{31-20} = 0xf57;
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}
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multiclass MemB<bits<4> op7_4, string opc> {
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def st : AMBI<opc, "\tst"> {
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let Inst{7-4} = op7_4;
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let Inst{3-0} = 0b1110;
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}
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def ish : AMBI<opc, "\tish"> {
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let Inst{7-4} = op7_4;
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let Inst{3-0} = 0b1011;
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}
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def ishst : AMBI<opc, "\tishst"> {
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let Inst{7-4} = op7_4;
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let Inst{3-0} = 0b1010;
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}
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def nsh : AMBI<opc, "\tnsh"> {
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let Inst{7-4} = op7_4;
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let Inst{3-0} = 0b0111;
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}
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def nshst : AMBI<opc, "\tnshst"> {
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let Inst{7-4} = op7_4;
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let Inst{3-0} = 0b0110;
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}
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def osh : AMBI<opc, "\tosh"> {
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let Inst{7-4} = op7_4;
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let Inst{3-0} = 0b0011;
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}
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def oshst : AMBI<opc, "\toshst"> {
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let Inst{7-4} = op7_4;
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let Inst{3-0} = 0b0010;
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}
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}
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// These DMB variants are for disassembly only.
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defm DMB : MemB<0b0101, "dmb">;
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// These DSB variants are for disassembly only.
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defm DSB : MemB<0b0100, "dsb">;
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// ISB has only full system option -- for disassembly only
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def ISBsy : AMBI<"isb", ""> {
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let Inst{7-4} = 0b0110;
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let Inst{3-0} = 0b1111;
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}
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let usesCustomInserter = 1 in {
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let Uses = [CPSR] in {
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def ATOMIC_LOAD_ADD_I8 : PseudoInst<
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