diff --git a/lld/ELF/InputSection.cpp b/lld/ELF/InputSection.cpp
index 6bb68bbf672d..1bf67e2a3380 100644
--- a/lld/ELF/InputSection.cpp
+++ b/lld/ELF/InputSection.cpp
@@ -470,7 +470,7 @@ void InputSection::copyRelocations(uint8_t *Buf, ArrayRef<RelTy> Rels) {
 
       if (RelTy::IsRela)
         P->r_addend = Sym.getVA(Addend) - Section->getOutputSection()->Addr;
-      else if (Config->Relocatable)
+      else if (Config->Relocatable && Type != Target->NoneRel)
         Sec->Relocations.push_back({R_ABS, Type, Rel.r_offset, Addend, &Sym});
     }
   }
diff --git a/lld/test/ELF/relocation-none-arm.s b/lld/test/ELF/relocation-none-arm.s
index 7251db26e880..9ca2b3801dc6 100644
--- a/lld/test/ELF/relocation-none-arm.s
+++ b/lld/test/ELF/relocation-none-arm.s
@@ -8,6 +8,13 @@
 # CHECK: .data
 # CHECK: There are no relocations in this file.
 
+# RUN: ld.lld -r %t.o -o %t
+# RUN: llvm-readobj -r %t | FileCheck --check-prefix=RELOC %s
+
+# RELOC:      Section ({{.*}}) .rel.text {
+# RELOC-NEXT:   0x0 R_ARM_NONE .data 0x0
+# RELOC-NEXT: }
+
 .globl _start
 _start:
   nop
diff --git a/lld/test/ELF/relocation-none-i386.s b/lld/test/ELF/relocation-none-i386.s
index f56f63644a65..812150772f42 100644
--- a/lld/test/ELF/relocation-none-i386.s
+++ b/lld/test/ELF/relocation-none-i386.s
@@ -8,6 +8,13 @@
 # CHECK: .data
 # CHECK: There are no relocations in this file.
 
+# RUN: ld.lld -r %t.o -o %t
+# RUN: llvm-readobj -r %t | FileCheck --check-prefix=RELOC %s
+
+# RELOC:      Section ({{.*}}) .rel.text {
+# RELOC-NEXT:   0x0 R_386_NONE .data 0x0
+# RELOC-NEXT: }
+
 .globl _start
 _start:
   ret