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[Target] Remove redundant member initialization (NFC) 

Identified with readability-redundant-member-init.
This commit is contained in:
Kazu Hirata 2022-01-06 22:01:44 -08:00
parent 6bcb4c44de
commit f3a344d212
47 changed files with 67 additions and 83 deletions
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3
llvm/lib/Target/AArch64/AArch64Subtarget.cpp
View File

@ -234,8 +234,7 @@ AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
IsLittle(LittleEndian),
MinSVEVectorSizeInBits(MinSVEVectorSizeInBitsOverride),
MaxSVEVectorSizeInBits(MaxSVEVectorSizeInBitsOverride), TargetTriple(TT),
FrameLowering(),
InstrInfo(initializeSubtargetDependencies(FS, CPU, TuneCPU)), TSInfo(),
InstrInfo(initializeSubtargetDependencies(FS, CPU, TuneCPU)),
TLInfo(TM, *this) {
if (AArch64::isX18ReservedByDefault(TT))
ReserveXRegister.set(18);

3
llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp
View File

@ -25,8 +25,7 @@ void AArch64_ELFTargetObjectFile::Initialize(MCContext &Ctx,
SupportDebugThreadLocalLocation = false;
}
AArch64_MachoTargetObjectFile::AArch64_MachoTargetObjectFile()
: TargetLoweringObjectFileMachO() {
AArch64_MachoTargetObjectFile::AArch64_MachoTargetObjectFile() {
SupportGOTPCRelWithOffset = false;
}

4
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
View File

@ -472,8 +472,8 @@ private:
AArch64InstructionSelector::AArch64InstructionSelector(
const AArch64TargetMachine &TM, const AArch64Subtarget &STI,
const AArch64RegisterBankInfo &RBI)
: InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()),
TRI(*STI.getRegisterInfo()), RBI(RBI),
: TM(TM), STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()),
RBI(RBI),
#define GET_GLOBALISEL_PREDICATES_INIT
#include "AArch64GenGlobalISel.inc"
#undef GET_GLOBALISEL_PREDICATES_INIT

2
llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.h
View File

@ -26,7 +26,7 @@ class AMDGPUAAResult : public AAResultBase<AMDGPUAAResult> {
const DataLayout &DL;
public:
explicit AMDGPUAAResult(const DataLayout &DL) : AAResultBase(), DL(DL) {}
explicit AMDGPUAAResult(const DataLayout &DL) : DL(DL) {}
AMDGPUAAResult(AMDGPUAAResult &&Arg)
: AAResultBase(std::move(Arg)), DL(Arg.DL) {}

3
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
View File

@ -46,8 +46,7 @@ static cl::opt<bool> AllowRiskySelect(
AMDGPUInstructionSelector::AMDGPUInstructionSelector(
const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI,
const AMDGPUTargetMachine &TM)
: InstructionSelector(), TII(*STI.getInstrInfo()),
TRI(*STI.getRegisterInfo()), RBI(RBI), TM(TM),
: TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI), TM(TM),
STI(STI),
EnableLateStructurizeCFG(AMDGPUTargetMachine::EnableLateStructurizeCFG),
#define GET_GLOBALISEL_PREDICATES_INIT

5
llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
View File

@ -15,9 +15,8 @@
using namespace llvm;
AMDGPUMachineFunction::AMDGPUMachineFunction(const MachineFunction &MF)
: MachineFunctionInfo(), Mode(MF.getFunction()),
IsEntryFunction(
AMDGPU::isEntryFunctionCC(MF.getFunction().getCallingConv())),
: Mode(MF.getFunction()), IsEntryFunction(AMDGPU::isEntryFunctionCC(
MF.getFunction().getCallingConv())),
IsModuleEntryFunction(
AMDGPU::isModuleEntryFunctionCC(MF.getFunction().getCallingConv())),
NoSignedZerosFPMath(MF.getTarget().Options.NoSignedZerosFPMath) {

2
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
View File

@ -62,7 +62,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
public:
AMDGPUOperand(KindTy Kind_, const AMDGPUAsmParser *AsmParser_)
: MCParsedAsmOperand(), Kind(Kind_), AsmParser(AsmParser_) {}
: Kind(Kind_), AsmParser(AsmParser_) {}
using Ptr = std::unique_ptr<AMDGPUOperand>;

3
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
View File

@ -15,8 +15,7 @@
using namespace llvm;
AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT,
const MCTargetOptions &Options)
: MCAsmInfoELF() {
const MCTargetOptions &Options) {
CodePointerSize = (TT.getArch() == Triple::amdgcn) ? 8 : 4;
StackGrowsUp = true;
HasSingleParameterDotFile = false;

2
llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
View File

@ -164,7 +164,7 @@ static bool getBaseOffset(const MachineInstr &MI, const MachineOperand *&BaseOp,
ARMBankConflictHazardRecognizer::ARMBankConflictHazardRecognizer(
const ScheduleDAG *DAG, int64_t CPUBankMask, bool CPUAssumeITCMConflict)
: ScheduleHazardRecognizer(), MF(DAG->MF), DL(DAG->MF.getDataLayout()),
: MF(DAG->MF), DL(DAG->MF.getDataLayout()),
DataMask(DataBankMask.getNumOccurrences() ? int64_t(DataBankMask)
: CPUBankMask),
AssumeITCMBankConflict(AssumeITCMConflict.getNumOccurrences()

2
llvm/lib/Target/ARM/ARMHazardRecognizer.h
View File

@ -34,7 +34,7 @@ class ARMHazardRecognizerFPMLx : public ScheduleHazardRecognizer {
unsigned FpMLxStalls = 0;
public:
ARMHazardRecognizerFPMLx() : ScheduleHazardRecognizer() { MaxLookAhead = 1; }
ARMHazardRecognizerFPMLx() { MaxLookAhead = 1; }
HazardType getHazardType(SUnit *SU, int Stalls) override;
void Reset() override;

3
llvm/lib/Target/ARM/ARMInstrInfo.cpp
View File

@ -28,8 +28,7 @@
#include "llvm/MC/MCInst.h"
using namespace llvm;
ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
: ARMBaseInstrInfo(STI), RI() {}
ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI) : ARMBaseInstrInfo(STI) {}
/// Return the noop instruction to use for a noop.
MCInst ARMInstrInfo::getNop() const {

4
llvm/lib/Target/ARM/ARMInstructionSelector.cpp
View File

@ -171,8 +171,8 @@ createARMInstructionSelector(const ARMBaseTargetMachine &TM,
ARMInstructionSelector::ARMInstructionSelector(const ARMBaseTargetMachine &TM,
const ARMSubtarget &STI,
const ARMRegisterBankInfo &RBI)
: InstructionSelector(), TII(*STI.getInstrInfo()),
TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), Opcodes(STI),
: TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI),
STI(STI), Opcodes(STI),
#define GET_GLOBALISEL_PREDICATES_INIT
#include "ARMGenGlobalISel.inc"
#undef GET_GLOBALISEL_PREDICATES_INIT

2
llvm/lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -15,4 +15,4 @@ using namespace llvm;
void ARMRegisterInfo::anchor() { }
ARMRegisterInfo::ARMRegisterInfo() : ARMBaseRegisterInfo() {}
ARMRegisterInfo::ARMRegisterInfo() {}

3
llvm/lib/Target/ARM/ARMTargetObjectFile.h
View File

@ -17,8 +17,7 @@ namespace llvm {
class ARMElfTargetObjectFile : public TargetLoweringObjectFileELF {
public:
ARMElfTargetObjectFile()
: TargetLoweringObjectFileELF() {
ARMElfTargetObjectFile() {
PLTRelativeVariantKind = MCSymbolRefExpr::VK_ARM_PREL31;
}

2
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -921,7 +921,7 @@ class ARMOperand : public MCParsedAsmOperand {
};
public:
ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
ARMOperand(KindTy K) : Kind(K) {}
/// getStartLoc - Get the location of the first token of this operand.
SMLoc getStartLoc() const override { return StartLoc; }

2
llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
View File

@ -21,7 +21,7 @@
using namespace llvm;
Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
: ARMBaseInstrInfo(STI), RI() {}
: ARMBaseInstrInfo(STI) {}
/// Return the noop instruction to use for a noop.
MCInst Thumb1InstrInfo::getNop() const {

2
llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
View File

@ -37,7 +37,7 @@ extern cl::opt<bool> ReuseFrameIndexVals;
using namespace llvm;
ThumbRegisterInfo::ThumbRegisterInfo() : ARMBaseRegisterInfo() {}
ThumbRegisterInfo::ThumbRegisterInfo() {}
const TargetRegisterClass *
ThumbRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,

3
llvm/lib/Target/AVR/AVRSubtarget.cpp
View File

@ -40,8 +40,7 @@ AVRSubtarget::AVRSubtarget(const Triple &TT, const std::string &CPU,
m_hasTinyEncoding(false), m_hasMemMappedGPR(false),
m_FeatureSetDummy(false),
InstrInfo(), FrameLowering(),
TLInfo(TM, initializeSubtargetDependencies(CPU, FS, TM)), TSInfo() {
TLInfo(TM, initializeSubtargetDependencies(CPU, FS, TM)) {
// Parse features string.
ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS);
}

8
llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
View File

@ -107,13 +107,13 @@ class AVROperand : public MCParsedAsmOperand {
public:
AVROperand(StringRef Tok, SMLoc const &S)
: Base(), Kind(k_Token), Tok(Tok), Start(S), End(S) {}
: Kind(k_Token), Tok(Tok), Start(S), End(S) {}
AVROperand(unsigned Reg, SMLoc const &S, SMLoc const &E)
: Base(), Kind(k_Register), RegImm({Reg, nullptr}), Start(S), End(E) {}
: Kind(k_Register), RegImm({Reg, nullptr}), Start(S), End(E) {}
AVROperand(MCExpr const *Imm, SMLoc const &S, SMLoc const &E)
: Base(), Kind(k_Immediate), RegImm({0, Imm}), Start(S), End(E) {}
: Kind(k_Immediate), RegImm({0, Imm}), Start(S), End(E) {}
AVROperand(unsigned Reg, MCExpr const *Imm, SMLoc const &S, SMLoc const &E)
: Base(), Kind(k_Memri), RegImm({Reg, Imm}), Start(S), End(E) {}
: Kind(k_Memri), RegImm({Reg, Imm}), Start(S), End(E) {}
struct RegisterImmediate {
unsigned Reg;

2
llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
View File

@ -101,7 +101,7 @@ struct BPFOperand : public MCParsedAsmOperand {
ImmOp Imm;
};
BPFOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
BPFOperand(KindTy K) : Kind(K) {}
public:
BPFOperand(const BPFOperand &o) : MCParsedAsmOperand() {

2
llvm/lib/Target/BPF/BPFSubtarget.cpp
View File

@ -59,6 +59,6 @@ void BPFSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
BPFSubtarget::BPFSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM)
: BPFGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), InstrInfo(),
: BPFGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
FrameLowering(initializeSubtargetDependencies(CPU, FS)),
TLInfo(TM, *this) {}

3
llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
View File

@ -211,8 +211,7 @@ struct HexagonOperand : public MCParsedAsmOperand {
struct ImmTy Imm;
};
HexagonOperand(KindTy K, MCContext &Context)
: MCParsedAsmOperand(), Kind(K), Context(Context) {}
HexagonOperand(KindTy K, MCContext &Context) : Kind(K), Context(Context) {}
public:
HexagonOperand(const HexagonOperand &o)

5
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
View File

@ -204,7 +204,7 @@ HexagonMCChecker::HexagonMCChecker(MCContext &Context, MCInstrInfo const &MCII,
MCSubtargetInfo const &STI, MCInst &mcb,
MCRegisterInfo const &ri, bool ReportErrors)
: Context(Context), MCB(mcb), RI(ri), MCII(MCII), STI(STI),
ReportErrors(ReportErrors), ReversePairs() {
ReportErrors(ReportErrors) {
init();
}
@ -212,8 +212,7 @@ HexagonMCChecker::HexagonMCChecker(HexagonMCChecker const &Other,
MCSubtargetInfo const &STI,
bool CopyReportErrors)
: Context(Other.Context), MCB(Other.MCB), RI(Other.RI), MCII(Other.MCII),
STI(STI), ReportErrors(CopyReportErrors ? Other.ReportErrors : false),
ReversePairs() {
STI(STI), ReportErrors(CopyReportErrors ? Other.ReportErrors : false) {
init();
}

2
llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
View File

@ -141,7 +141,7 @@ struct LanaiOperand : public MCParsedAsmOperand {
struct MemOp Mem;
};
explicit LanaiOperand(KindTy Kind) : MCParsedAsmOperand(), Kind(Kind) {}
explicit LanaiOperand(KindTy Kind) : Kind(Kind) {}
public:
// The functions below are used by the autogenerated ASM matcher and hence to

2
llvm/lib/Target/Lanai/LanaiSubtarget.cpp
View File

@ -43,4 +43,4 @@ LanaiSubtarget::LanaiSubtarget(const Triple &TargetTriple, StringRef Cpu,
CodeGenOpt::Level /*OptLevel*/)
: LanaiGenSubtargetInfo(TargetTriple, Cpu, /*TuneCPU*/ Cpu, FeatureString),
FrameLowering(initializeSubtargetDependencies(Cpu, FeatureString)),
InstrInfo(), TLInfo(TM, *this), TSInfo() {}
TLInfo(TM, *this) {}

11
llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
View File

@ -114,13 +114,14 @@ class MSP430Operand : public MCParsedAsmOperand {
public:
MSP430Operand(StringRef Tok, SMLoc const &S)
: Base(), Kind(k_Tok), Tok(Tok), Start(S), End(S) {}
: Kind(k_Tok), Tok(Tok), Start(S), End(S) {}
MSP430Operand(KindTy Kind, unsigned Reg, SMLoc const &S, SMLoc const &E)
: Base(), Kind(Kind), Reg(Reg), Start(S), End(E) {}
: Kind(Kind), Reg(Reg), Start(S), End(E) {}
MSP430Operand(MCExpr const *Imm, SMLoc const &S, SMLoc const &E)
: Base(), Kind(k_Imm), Imm(Imm), Start(S), End(E) {}
MSP430Operand(unsigned Reg, MCExpr const *Expr, SMLoc const &S, SMLoc const &E)
: Base(), Kind(k_Mem), Mem({Reg, Expr}), Start(S), End(E) {}
: Kind(k_Imm), Imm(Imm), Start(S), End(E) {}
MSP430Operand(unsigned Reg, MCExpr const *Expr, SMLoc const &S,
SMLoc const &E)
: Kind(k_Mem), Mem({Reg, Expr}), Start(S), End(E) {}
void addRegOperands(MCInst &Inst, unsigned N) const {
assert((Kind == k_Reg || Kind == k_IndReg || Kind == k_PostIndReg) &&

2
llvm/lib/Target/MSP430/MSP430Subtarget.cpp
View File

@ -57,5 +57,5 @@ MSP430Subtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
MSP430Subtarget::MSP430Subtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM)
: MSP430GenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), FrameLowering(),
: MSP430GenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this) {}

3
llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@ -827,8 +827,7 @@ private:
} Kind;
public:
MipsOperand(KindTy K, MipsAsmParser &Parser)
: MCParsedAsmOperand(), Kind(K), AsmParser(Parser) {}
MipsOperand(KindTy K, MipsAsmParser &Parser) : Kind(K), AsmParser(Parser) {}
~MipsOperand() override {
switch (Kind) {

2
llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
View File

@ -37,7 +37,7 @@ using namespace llvm;
#define DEBUG_TYPE "mips16-registerinfo"
Mips16RegisterInfo::Mips16RegisterInfo() : MipsRegisterInfo() {}
Mips16RegisterInfo::Mips16RegisterInfo() {}
bool Mips16RegisterInfo::requiresRegisterScavenging
(const MachineFunction &MF) const {

4
llvm/lib/Target/Mips/MipsInstructionSelector.cpp
View File

@ -80,8 +80,8 @@ private:
MipsInstructionSelector::MipsInstructionSelector(
const MipsTargetMachine &TM, const MipsSubtarget &STI,
const MipsRegisterBankInfo &RBI)
: InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()),
TRI(*STI.getRegisterInfo()), RBI(RBI),
: TM(TM), STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()),
RBI(RBI),
#define GET_GLOBALISEL_PREDICATES_INIT
#include "MipsGenGlobalISel.inc"

2
llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
View File

@ -38,7 +38,7 @@ using namespace llvm;
#define DEBUG_TYPE "mips-reg-info"
MipsSERegisterInfo::MipsSERegisterInfo() : MipsRegisterInfo() {}
MipsSERegisterInfo::MipsSERegisterInfo() {}
bool MipsSERegisterInfo::
requiresRegisterScavenging(const MachineFunction &MF) const {

4
llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
View File

@ -49,8 +49,8 @@ NVPTXSubtarget::NVPTXSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS,
const NVPTXTargetMachine &TM)
: NVPTXGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), PTXVersion(0),
SmVersion(20), TM(TM), InstrInfo(),
TLInfo(TM, initializeSubtargetDependencies(CPU, FS)), FrameLowering() {}
SmVersion(20), TM(TM),
TLInfo(TM, initializeSubtargetDependencies(CPU, FS)) {}
bool NVPTXSubtarget::hasImageHandles() const {
// Enable handles for Kepler+, where CUDA supports indirect surfaces and

2
llvm/lib/Target/NVPTX/NVPTXTargetObjectFile.h
View File

@ -17,7 +17,7 @@ namespace llvm {
class NVPTXTargetObjectFile : public TargetLoweringObjectFile {
public:
NVPTXTargetObjectFile() : TargetLoweringObjectFile() {}
NVPTXTargetObjectFile() {}
~NVPTXTargetObjectFile() override;

3
llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
View File

@ -201,7 +201,8 @@ struct PPCOperand : public MCParsedAsmOperand {
struct TLSRegOp TLSReg;
};
PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
PPCOperand(KindTy K) : Kind(K) {}
public:
PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
Kind = o.Kind;

3
llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
View File

@ -65,8 +65,7 @@ private:
PPCInstructionSelector::PPCInstructionSelector(const PPCTargetMachine &TM,
const PPCSubtarget &STI,
const PPCRegisterBankInfo &RBI)
: InstructionSelector(), TII(*STI.getInstrInfo()),
TRI(*STI.getRegisterInfo()), RBI(RBI),
: TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI),
#define GET_GLOBALISEL_PREDICATES_INIT
#include "PPCGenGlobalISel.inc"
#undef GET_GLOBALISEL_PREDICATES_INIT

2
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
View File

@ -302,7 +302,7 @@ struct RISCVOperand : public MCParsedAsmOperand {
struct VTypeOp VType;
};
RISCVOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
RISCVOperand(KindTy K) : Kind(K) {}
public:
RISCVOperand(const RISCVOperand &o) : MCParsedAsmOperand() {

3
llvm/lib/Target/RISCV/RISCVInstructionSelector.cpp
View File

@ -69,8 +69,7 @@ private:
RISCVInstructionSelector::RISCVInstructionSelector(
const RISCVTargetMachine &TM, const RISCVSubtarget &STI,
const RISCVRegisterBankInfo &RBI)
: InstructionSelector(), STI(STI), TII(*STI.getInstrInfo()),
TRI(*STI.getRegisterInfo()), RBI(RBI),
: STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI),
#define GET_GLOBALISEL_PREDICATES_INIT
#include "RISCVGenGlobalISel.inc"

2
llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
View File

@ -257,7 +257,7 @@ private:
};
public:
SparcOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
SparcOperand(KindTy K) : Kind(K) {}
bool isToken() const override { return Kind == k_Token; }
bool isReg() const override { return Kind == k_Register; }

4
llvm/lib/Target/Sparc/SparcTargetObjectFile.h
View File

@ -18,9 +18,7 @@ class TargetMachine;
class SparcELFTargetObjectFile : public TargetLoweringObjectFileELF {
public:
SparcELFTargetObjectFile() :
TargetLoweringObjectFileELF()
{}
SparcELFTargetObjectFile() {}
void Initialize(MCContext &Ctx, const TargetMachine &TM) override;

3
llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
View File

@ -62,8 +62,7 @@ struct SystemZAddressingMode {
bool IncludesDynAlloc;
SystemZAddressingMode(AddrForm form, DispRange dr)
: Form(form), DR(dr), Base(), Disp(0), Index(),
IncludesDynAlloc(false) {}
: Form(form), DR(dr), Disp(0), IncludesDynAlloc(false) {}
// True if the address can have an index register.
bool hasIndexField() { return Form != FormBD; }

2
llvm/lib/Target/SystemZ/SystemZSubtarget.cpp
View File

@ -89,7 +89,7 @@ SystemZSubtarget::SystemZSubtarget(const Triple &TT, const std::string &CPU,
HasSoftFloat(false), TargetTriple(TT),
SpecialRegisters(initializeSpecialRegisters()),
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
TSInfo(), FrameLowering(SystemZFrameLowering::create(*this)) {}
FrameLowering(SystemZFrameLowering::create(*this)) {}
bool SystemZSubtarget::enableSubRegLiveness() const {
return UseSubRegLiveness;

2
llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
View File

@ -210,7 +210,7 @@ private:
};
public:
VEOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
VEOperand(KindTy K) : Kind(K) {}
bool isToken() const override { return Kind == k_Token; }
bool isReg() const override { return Kind == k_Register; }

5
llvm/lib/Target/VE/VEMachineFunctionInfo.h
View File

@ -29,10 +29,9 @@ private:
bool IsLeafProc;
public:
VEMachineFunctionInfo()
: GlobalBaseReg(), VarArgsFrameOffset(0), IsLeafProc(false) {}
VEMachineFunctionInfo() : VarArgsFrameOffset(0), IsLeafProc(false) {}
explicit VEMachineFunctionInfo(MachineFunction &MF)
: GlobalBaseReg(), VarArgsFrameOffset(0), IsLeafProc(false) {}
: VarArgsFrameOffset(0), IsLeafProc(false) {}
Register getGlobalBaseReg() const { return GlobalBaseReg; }
void setGlobalBaseReg(Register Reg) { GlobalBaseReg = Reg; }

3
llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp
View File

@ -42,8 +42,7 @@ WebAssemblySubtarget::WebAssemblySubtarget(const Triple &TT,
const std::string &FS,
const TargetMachine &TM)
: WebAssemblyGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
TargetTriple(TT), FrameLowering(),
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TSInfo(),
TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
TLInfo(TM, *this) {}
bool WebAssemblySubtarget::enableAtomicExpand() const {

6
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -80,9 +80,9 @@ namespace {
bool NegateIndex = false;
X86ISelAddressMode()
: BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
Segment(), GV(nullptr), CP(nullptr), BlockAddr(nullptr), ES(nullptr),
MCSym(nullptr), JT(-1), SymbolFlags(X86II::MO_NO_FLAG) {}
: BaseType(RegBase), Base_FrameIndex(0), Scale(1), Disp(0), GV(nullptr),
CP(nullptr), BlockAddr(nullptr), ES(nullptr), MCSym(nullptr), JT(-1),
SymbolFlags(X86II::MO_NO_FLAG) {}
bool hasSymbolicDisplacement() const {
return GV != nullptr || CP != nullptr || ES != nullptr ||

4
llvm/lib/Target/X86/X86InstructionSelector.cpp
View File

@ -153,8 +153,8 @@ private:
X86InstructionSelector::X86InstructionSelector(const X86TargetMachine &TM,
const X86Subtarget &STI,
const X86RegisterBankInfo &RBI)
: InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()),
TRI(*STI.getRegisterInfo()), RBI(RBI),
: TM(TM), STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()),
RBI(RBI),
#define GET_GLOBALISEL_PREDICATES_INIT
#include "X86GenGlobalISel.inc"
#undef GET_GLOBALISEL_PREDICATES_INIT

4
llvm/lib/Target/XCore/XCoreSubtarget.cpp
View File

@ -26,5 +26,5 @@ void XCoreSubtarget::anchor() { }
XCoreSubtarget::XCoreSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM)
: XCoreGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), InstrInfo(),
FrameLowering(*this), TLInfo(TM, *this), TSInfo() {}
: XCoreGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), FrameLowering(*this),
TLInfo(TM, *this) {}