forked from OSchip/llvm-project
[AMDGPU] Fix 224-bit spills
Related to D104622. Differential Revision: https://reviews.llvm.org/D105109
This commit is contained in:
Piotr Sobczak
parent
aaf6a7ac34
commit
f38a8b54ea
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@ -1394,6 +1394,8 @@ static unsigned getAGPRSpillSaveOpcode(unsigned Size) {
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return AMDGPU::SI_SPILL_A160_SAVE;
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case 24:
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return AMDGPU::SI_SPILL_A192_SAVE;
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case 28:
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return AMDGPU::SI_SPILL_A224_SAVE;
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case 32:
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return AMDGPU::SI_SPILL_A256_SAVE;
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case 64:
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@ -1531,6 +1533,8 @@ static unsigned getAGPRSpillRestoreOpcode(unsigned Size) {
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return AMDGPU::SI_SPILL_A160_RESTORE;
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case 24:
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return AMDGPU::SI_SPILL_A192_RESTORE;
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case 28:
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return AMDGPU::SI_SPILL_A224_RESTORE;
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case 32:
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return AMDGPU::SI_SPILL_A256_RESTORE;
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case 64:
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@ -814,6 +814,13 @@ static unsigned getNumSubRegsForSpillOp(unsigned Op) {
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case AMDGPU::SI_SPILL_A256_SAVE:
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case AMDGPU::SI_SPILL_A256_RESTORE:
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return 8;
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case AMDGPU::SI_SPILL_S224_SAVE:
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case AMDGPU::SI_SPILL_S224_RESTORE:
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case AMDGPU::SI_SPILL_V224_SAVE:
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case AMDGPU::SI_SPILL_V224_RESTORE:
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case AMDGPU::SI_SPILL_A224_SAVE:
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case AMDGPU::SI_SPILL_A224_RESTORE:
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return 7;
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case AMDGPU::SI_SPILL_S192_SAVE:
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case AMDGPU::SI_SPILL_S192_RESTORE:
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case AMDGPU::SI_SPILL_V192_SAVE:
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@ -1473,6 +1480,7 @@ bool SIRegisterInfo::eliminateSGPRToVGPRSpillFrameIndex(
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case AMDGPU::SI_SPILL_S1024_SAVE:
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case AMDGPU::SI_SPILL_S512_SAVE:
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case AMDGPU::SI_SPILL_S256_SAVE:
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case AMDGPU::SI_SPILL_S224_SAVE:
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case AMDGPU::SI_SPILL_S192_SAVE:
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case AMDGPU::SI_SPILL_S160_SAVE:
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case AMDGPU::SI_SPILL_S128_SAVE:
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@ -1483,6 +1491,7 @@ bool SIRegisterInfo::eliminateSGPRToVGPRSpillFrameIndex(
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case AMDGPU::SI_SPILL_S1024_RESTORE:
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case AMDGPU::SI_SPILL_S512_RESTORE:
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case AMDGPU::SI_SPILL_S256_RESTORE:
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case AMDGPU::SI_SPILL_S224_RESTORE:
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case AMDGPU::SI_SPILL_S192_RESTORE:
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case AMDGPU::SI_SPILL_S160_RESTORE:
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case AMDGPU::SI_SPILL_S128_RESTORE:
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@ -1519,6 +1528,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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case AMDGPU::SI_SPILL_S1024_SAVE:
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case AMDGPU::SI_SPILL_S512_SAVE:
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case AMDGPU::SI_SPILL_S256_SAVE:
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case AMDGPU::SI_SPILL_S224_SAVE:
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case AMDGPU::SI_SPILL_S192_SAVE:
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case AMDGPU::SI_SPILL_S160_SAVE:
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case AMDGPU::SI_SPILL_S128_SAVE:
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@ -1533,6 +1543,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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case AMDGPU::SI_SPILL_S1024_RESTORE:
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case AMDGPU::SI_SPILL_S512_RESTORE:
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case AMDGPU::SI_SPILL_S256_RESTORE:
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case AMDGPU::SI_SPILL_S224_RESTORE:
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case AMDGPU::SI_SPILL_S192_RESTORE:
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case AMDGPU::SI_SPILL_S160_RESTORE:
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case AMDGPU::SI_SPILL_S128_RESTORE:
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@ -1547,6 +1558,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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case AMDGPU::SI_SPILL_V1024_SAVE:
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case AMDGPU::SI_SPILL_V512_SAVE:
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case AMDGPU::SI_SPILL_V256_SAVE:
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case AMDGPU::SI_SPILL_V224_SAVE:
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case AMDGPU::SI_SPILL_V192_SAVE:
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case AMDGPU::SI_SPILL_V160_SAVE:
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case AMDGPU::SI_SPILL_V128_SAVE:
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@ -1556,6 +1568,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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case AMDGPU::SI_SPILL_A1024_SAVE:
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case AMDGPU::SI_SPILL_A512_SAVE:
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case AMDGPU::SI_SPILL_A256_SAVE:
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case AMDGPU::SI_SPILL_A224_SAVE:
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case AMDGPU::SI_SPILL_A192_SAVE:
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case AMDGPU::SI_SPILL_A160_SAVE:
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case AMDGPU::SI_SPILL_A128_SAVE:
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@ -1584,6 +1597,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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case AMDGPU::SI_SPILL_V128_RESTORE:
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case AMDGPU::SI_SPILL_V160_RESTORE:
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case AMDGPU::SI_SPILL_V192_RESTORE:
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case AMDGPU::SI_SPILL_V224_RESTORE:
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case AMDGPU::SI_SPILL_V256_RESTORE:
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case AMDGPU::SI_SPILL_V512_RESTORE:
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case AMDGPU::SI_SPILL_V1024_RESTORE:
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@ -1593,6 +1607,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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case AMDGPU::SI_SPILL_A128_RESTORE:
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case AMDGPU::SI_SPILL_A160_RESTORE:
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case AMDGPU::SI_SPILL_A192_RESTORE:
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case AMDGPU::SI_SPILL_A224_RESTORE:
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case AMDGPU::SI_SPILL_A256_RESTORE:
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case AMDGPU::SI_SPILL_A512_RESTORE:
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case AMDGPU::SI_SPILL_A1024_RESTORE: {
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@ -0,0 +1,104 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=regallocfast -o - %s | FileCheck -check-prefix=SPILLED %s
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=regallocfast,si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=EXPANDED %s
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# Make sure spill/restore of 224 bit registers works.
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---
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name: spill_restore_sgpr224
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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stackPtrOffsetReg: $sgpr32
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body: |
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; SPILLED-LABEL: name: spill_restore_sgpr224
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; SPILLED: bb.0:
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; SPILLED: successors: %bb.1(0x80000000)
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; SPILLED: S_NOP 0, implicit-def renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10
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; SPILLED: SI_SPILL_S224_SAVE killed $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10, %stack.0, implicit $exec, implicit $sgpr32 :: (store 28 into %stack.0, align 4, addrspace 5)
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; SPILLED: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
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; SPILLED: bb.1:
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; SPILLED: successors: %bb.2(0x80000000)
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; SPILLED: S_NOP 1
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; SPILLED: bb.2:
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; SPILLED: $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10 = SI_SPILL_S224_RESTORE %stack.0, implicit $exec, implicit $sgpr32 :: (load 28 from %stack.0, align 4, addrspace 5)
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; SPILLED: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10
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; EXPANDED-LABEL: name: spill_restore_sgpr224
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; EXPANDED: bb.0:
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; EXPANDED: successors: %bb.1(0x80000000)
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; EXPANDED: liveins: $vgpr0
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; EXPANDED: S_NOP 0, implicit-def renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10
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; EXPANDED: $vgpr0 = V_WRITELANE_B32 $sgpr4, 0, $vgpr0, implicit-def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10, implicit $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10
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; EXPANDED: $vgpr0 = V_WRITELANE_B32 $sgpr5, 1, $vgpr0, implicit $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10
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; EXPANDED: $vgpr0 = V_WRITELANE_B32 $sgpr6, 2, $vgpr0, implicit $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10
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; EXPANDED: $vgpr0 = V_WRITELANE_B32 $sgpr7, 3, $vgpr0, implicit $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10
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; EXPANDED: $vgpr0 = V_WRITELANE_B32 $sgpr8, 4, $vgpr0, implicit $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10
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; EXPANDED: $vgpr0 = V_WRITELANE_B32 $sgpr9, 5, $vgpr0, implicit $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10
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; EXPANDED: $vgpr0 = V_WRITELANE_B32 killed $sgpr10, 6, $vgpr0, implicit killed $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10
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; EXPANDED: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
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; EXPANDED: bb.1:
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; EXPANDED: successors: %bb.2(0x80000000)
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; EXPANDED: liveins: $vgpr0
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; EXPANDED: S_NOP 1
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; EXPANDED: bb.2:
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; EXPANDED: liveins: $vgpr0
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; EXPANDED: $sgpr4 = V_READLANE_B32 $vgpr0, 0, implicit-def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10
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; EXPANDED: $sgpr5 = V_READLANE_B32 $vgpr0, 1
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; EXPANDED: $sgpr6 = V_READLANE_B32 $vgpr0, 2
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; EXPANDED: $sgpr7 = V_READLANE_B32 $vgpr0, 3
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; EXPANDED: $sgpr8 = V_READLANE_B32 $vgpr0, 4
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; EXPANDED: $sgpr9 = V_READLANE_B32 $vgpr0, 5
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; EXPANDED: $sgpr10 = V_READLANE_B32 $vgpr0, 6
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; EXPANDED: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10
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bb.0:
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S_NOP 0, implicit-def %0:sgpr_224
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S_CBRANCH_SCC1 implicit undef $scc, %bb.1
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bb.1:
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S_NOP 1
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bb.2:
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S_NOP 0, implicit %0
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...
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---
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name: spill_restore_vgpr224
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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stackPtrOffsetReg: $sgpr32
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body: |
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; SPILLED-LABEL: name: spill_restore_vgpr224
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; SPILLED: bb.0:
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; SPILLED: successors: %bb.1(0x80000000)
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; SPILLED: S_NOP 0, implicit-def renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
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; SPILLED: SI_SPILL_V224_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6, %stack.0, $sgpr32, 0, implicit $exec :: (store 28 into %stack.0, align 4, addrspace 5)
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; SPILLED: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
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; SPILLED: bb.1:
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; SPILLED: successors: %bb.2(0x80000000)
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; SPILLED: S_NOP 1
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; SPILLED: bb.2:
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; SPILLED: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 = SI_SPILL_V224_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 28 from %stack.0, align 4, addrspace 5)
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; SPILLED: S_NOP 0, implicit killed renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
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; EXPANDED-LABEL: name: spill_restore_vgpr224
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; EXPANDED: bb.0:
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; EXPANDED: successors: %bb.1(0x80000000)
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; EXPANDED: S_NOP 0, implicit-def renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
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; EXPANDED: SI_SPILL_V224_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6, %stack.0, $sgpr32, 0, implicit $exec :: (store 28 into %stack.0, align 4, addrspace 5)
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; EXPANDED: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
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; EXPANDED: bb.1:
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; EXPANDED: successors: %bb.2(0x80000000)
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; EXPANDED: S_NOP 1
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; EXPANDED: bb.2:
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; EXPANDED: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 = SI_SPILL_V224_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 28 from %stack.0, align 4, addrspace 5)
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; EXPANDED: S_NOP 0, implicit killed renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
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bb.0:
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S_NOP 0, implicit-def %0:vreg_224
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S_CBRANCH_SCC1 implicit undef $scc, %bb.1
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bb.1:
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S_NOP 1
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bb.2:
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S_NOP 0, implicit %0
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...
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