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RegisterPressure: Fix default lanemask for missing regunit intervals 

In case of missing live intervals for a physical registers
getLanesWithProperty() would report 0 which was not a safe default in
all situations. Add a parameter to pass in a safe default.
No testcase because in-tree targets do not skip computing register unit
live intervals.

Also cleanup the getXXX() functions to not perform the
RequireLiveIntervals checks anymore so we do not even need to return
safe defaults.

llvm-svn: 267977
This commit is contained in:
Matthias Braun 2016-04-29 02:44:54 +00:00
parent 5e4ac856d6
commit f3619b8212
3 changed files with 37 additions and 39 deletions
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38
llvm/lib/CodeGen/RegisterPressure.cpp
View File

@ -382,7 +382,7 @@ static void removeRegLanes(SmallVectorImpl<RegisterMaskPair> &RegUnits,
static LaneBitmask getLanesWithProperty(const LiveIntervals &LIS,
const MachineRegisterInfo &MRI, bool TrackLaneMasks, unsigned RegUnit,
SlotIndex Pos,
SlotIndex Pos, LaneBitmask SafeDefault,
bool(*Property)(const LiveRange &LR, SlotIndex Pos)) {
if (TargetRegisterInfo::isVirtualRegister(RegUnit)) {
const LiveInterval &LI = LIS.getInterval(RegUnit);
@ -402,7 +402,7 @@ static LaneBitmask getLanesWithProperty(const LiveIntervals &LIS,
// Be prepared for missing liveranges: We usually do not compute liveranges
// for physical registers on targets with many registers (GPUs).
if (LR == nullptr)
return 0;
return SafeDefault;
return Property(*LR, Pos) ? ~0u : 0;
}
}
@ -411,7 +411,7 @@ static LaneBitmask getLiveLanesAt(const LiveIntervals &LIS,
const MachineRegisterInfo &MRI,
bool TrackLaneMasks, unsigned RegUnit,
SlotIndex Pos) {
return getLanesWithProperty(LIS, MRI, TrackLaneMasks, RegUnit, Pos,
return getLanesWithProperty(LIS, MRI, TrackLaneMasks, RegUnit, Pos, ~0u,
[](const LiveRange &LR, SlotIndex Pos) {
return LR.liveAt(Pos);
});
@ -570,11 +570,11 @@ void RegisterOperands::adjustLaneLiveness(const LiveIntervals &LIS,
AddFlagsMI != nullptr && (LiveAfter & ~I->LaneMask) == 0)
AddFlagsMI->setRegisterDefReadUndef(RegUnit);
LaneBitmask LaneMask = I->LaneMask & LiveAfter;
if (LaneMask == 0) {
LaneBitmask ActualDef = I->LaneMask & LiveAfter;
if (ActualDef == 0) {
I = Defs.erase(I);
} else {
I->LaneMask = LaneMask;
I->LaneMask = ActualDef;
++I;
}
}
@ -790,10 +790,12 @@ void RegPressureTracker::recede(const RegisterOperands &RegOpers,
}
// Discover live outs if this may be the first occurance of this register.
if (RequireIntervals) {
LaneBitmask LiveOut = getLiveThroughAt(Reg, SlotIdx);
if (LiveOut != 0)
discoverLiveOut(RegisterMaskPair(Reg, LiveOut));
}
}
increaseRegPressure(Reg, PreviousMask, NewMask);
}
@ -875,12 +877,14 @@ void RegPressureTracker::advance(const RegisterOperands &RegOpers) {
LiveRegs.insert(RegisterMaskPair(Reg, LiveIn));
}
// Kill liveness at last uses.
if (RequireIntervals) {
LaneBitmask LastUseMask = getLastUsedLanes(Reg, SlotIdx);
if (LastUseMask != 0) {
LiveRegs.erase(RegisterMaskPair(Reg, LastUseMask));
decreaseRegPressure(Reg, LiveMask, LiveMask & ~LastUseMask);
}
}
}
// Generate liveness for defs.
for (const RegisterMaskPair &Def : RegOpers.Defs) {
@ -1197,10 +1201,8 @@ static LaneBitmask findUseBetween(unsigned Reg, LaneBitmask LastUseMask,
LaneBitmask RegPressureTracker::getLiveLanesAt(unsigned RegUnit,
SlotIndex Pos) const {
if (!RequireIntervals)
return 0;
return getLanesWithProperty(*LIS, *MRI, TrackLaneMasks, RegUnit, Pos,
assert(RequireIntervals);
return getLanesWithProperty(*LIS, *MRI, TrackLaneMasks, RegUnit, Pos, ~0u,
[](const LiveRange &LR, SlotIndex Pos) {
return LR.liveAt(Pos);
});
@ -1208,11 +1210,9 @@ LaneBitmask RegPressureTracker::getLiveLanesAt(unsigned RegUnit,
LaneBitmask RegPressureTracker::getLastUsedLanes(unsigned RegUnit,
SlotIndex Pos) const {
if (!RequireIntervals)
return 0;
assert(RequireIntervals);
return getLanesWithProperty(*LIS, *MRI, TrackLaneMasks, RegUnit,
Pos.getBaseIndex(),
Pos.getBaseIndex(), 0,
[](const LiveRange &LR, SlotIndex Pos) {
const LiveRange::Segment *S = LR.getSegmentContaining(Pos);
return S != nullptr && S->end == Pos.getRegSlot();
@ -1221,10 +1221,8 @@ LaneBitmask RegPressureTracker::getLastUsedLanes(unsigned RegUnit,
LaneBitmask RegPressureTracker::getLiveThroughAt(unsigned RegUnit,
SlotIndex Pos) const {
if (!RequireIntervals)
return 0;
return getLanesWithProperty(*LIS, *MRI, TrackLaneMasks, RegUnit, Pos,
assert(RequireIntervals);
return getLanesWithProperty(*LIS, *MRI, TrackLaneMasks, RegUnit, Pos, 0u,
[](const LiveRange &LR, SlotIndex Pos) {
const LiveRange::Segment *S = LR.getSegmentContaining(Pos);
return S != nullptr && S->start < Pos.getRegSlot(true) &&
@ -1251,12 +1249,12 @@ void RegPressureTracker::bumpDownwardPressure(const MachineInstr *MI) {
if (TrackLaneMasks)
RegOpers.adjustLaneLiveness(*LIS, *MRI, SlotIdx);
if (RequireIntervals) {
for (const RegisterMaskPair &Use : RegOpers.Uses) {
unsigned Reg = Use.RegUnit;
LaneBitmask LastUseMask = getLastUsedLanes(Reg, SlotIdx);
if (LastUseMask == 0)
continue;
if (RequireIntervals) {
// The LastUseMask is queried from the liveness information of instruction
// which may be further down the schedule. Some lanes may actually not be
// last uses for the current position.
@ -1267,12 +1265,12 @@ void RegPressureTracker::bumpDownwardPressure(const MachineInstr *MI) {
= findUseBetween(Reg, LastUseMask, CurrIdx, SlotIdx, *MRI, LIS);
if (LastUseMask == 0)
continue;
}
LaneBitmask LiveMask = LiveRegs.contains(Reg);
LaneBitmask NewMask = LiveMask & ~LastUseMask;
decreaseRegPressure(Reg, LiveMask, NewMask);
}
}
// Generate liveness for defs.
for (const RegisterMaskPair &Def : RegOpers.Defs) {

6
llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
View File

@ -1,10 +1,10 @@
; RUN: llc -march=amdgcn -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}stored_fi_to_lds:
; GCN-DAG: s_load_dword [[LDSPTR:s[0-9]+]]
; GCN-DAG: v_mov_b32_e32 [[ZERO1:v[0-9]+]], 0{{$}}
; GCN-DAG: buffer_store_dword v{{[0-9]+}}, [[ZERO1]]
; GCN: s_load_dword [[LDSPTR:s[0-9]+]]
; GCN: v_mov_b32_e32 [[ZERO0:v[0-9]+]], 0{{$}}
; GCN: v_mov_b32_e32 [[ZERO1:v[0-9]+]], 0{{$}}
; GCN: buffer_store_dword v{{[0-9]+}}, [[ZERO1]]
; GCN: v_mov_b32_e32 [[VLDSPTR:v[0-9]+]], [[LDSPTR]]
; GCN: ds_write_b32 [[VLDSPTR]], [[ZERO0]]
define void @stored_fi_to_lds(float* addrspace(3)* %ptr) #0 {

2
llvm/test/CodeGen/AMDGPU/valu-i1.ll
View File

@ -137,7 +137,7 @@ exit:
; SI: BB#4:
; SI: buffer_store_dword
; SI: v_cmp_ge_i64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]]
; SI: v_cmp_ge_i64_e32 [[CMP:s\[[0-9]+:[0-9]+\]|vcc]]
; SI: s_or_b64 [[TMP:s\[[0-9]+:[0-9]+\]]], [[CMP]], [[COND_STATE]]
; SI: BB3_5: