forked from OSchip/llvm-project
[LoongArch] Add codegen support for bswap
Differential Revision: https://reviews.llvm.org/D131352
This commit is contained in:
WANG Xuerui
Weining Lu
parent
e8c807fade
commit
f35cb7ba34
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@ -69,6 +69,14 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
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}
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// LA32 does not have REVB.2W and REVB.D due to the 64-bit operands, and
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// the narrower REVB.W does not exist. But LA32 does have REVB.2H, so i16
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// and i32 could still be byte-swapped relatively cheaply.
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setOperationAction(ISD::BSWAP, MVT::i16, Custom);
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if (Subtarget.is64Bit()) {
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setOperationAction(ISD::BSWAP, MVT::i32, Custom);
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}
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static const ISD::CondCode FPCCToExpand[] = {ISD::SETOGT, ISD::SETOGE,
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ISD::SETUGT, ISD::SETUGE};
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@ -131,6 +139,8 @@ SDValue LoongArchTargetLowering::LowerOperation(SDValue Op,
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assert(Op.getOperand(1).getValueType() == MVT::i32 && Subtarget.is64Bit() &&
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"Unexpected custom legalisation");
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return SDValue();
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case ISD::BSWAP:
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return SDValue();
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case ISD::ConstantPool:
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return lowerConstantPool(Op, DAG);
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case ISD::FP_TO_SINT:
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@ -418,6 +428,29 @@ void LoongArchTargetLowering::ReplaceNodeResults(
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Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Tmp1));
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break;
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}
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case ISD::BSWAP: {
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SDValue Src = N->getOperand(0);
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EVT VT = N->getValueType(0);
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assert((VT == MVT::i16 || VT == MVT::i32) &&
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"Unexpected custom legalization");
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MVT GRLenVT = Subtarget.getGRLenVT();
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SDValue NewSrc = DAG.getNode(ISD::ANY_EXTEND, DL, GRLenVT, Src);
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SDValue Tmp;
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switch (VT.getSizeInBits()) {
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default:
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llvm_unreachable("Unexpected operand width");
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case 16:
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Tmp = DAG.getNode(LoongArchISD::REVB_2H, DL, GRLenVT, NewSrc);
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break;
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case 32:
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// Only LA64 will get to here due to the size mismatch between VT and
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// GRLenVT, LA32 lowering is directly defined in LoongArchInstrInfo.
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Tmp = DAG.getNode(LoongArchISD::REVB_2W, DL, GRLenVT, NewSrc);
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break;
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}
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Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, Tmp));
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break;
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}
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}
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}
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@ -847,6 +880,8 @@ const char *LoongArchTargetLowering::getTargetNodeName(unsigned Opcode) const {
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NODE_NAME_CASE(MOVGR2FR_W_LA64)
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NODE_NAME_CASE(MOVFR2GR_S_LA64)
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NODE_NAME_CASE(FTINT)
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NODE_NAME_CASE(REVB_2H)
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NODE_NAME_CASE(REVB_2W)
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}
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#undef NODE_NAME_CASE
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return nullptr;
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@ -44,6 +44,9 @@ enum NodeType : unsigned {
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BSTRINS,
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BSTRPICK,
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// Byte swapping operations
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REVB_2H,
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REVB_2W,
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};
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} // end namespace LoongArchISD
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@ -55,6 +55,8 @@ def loongarch_bstrins
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: SDNode<"LoongArchISD::BSTRINS", SDT_LoongArchBStrIns>;
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def loongarch_bstrpick
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: SDNode<"LoongArchISD::BSTRPICK", SDT_LoongArchBStrPick>;
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def loongarch_revb_2h : SDNode<"LoongArchISD::REVB_2H", SDTUnaryOp>;
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def loongarch_revb_2w : SDNode<"LoongArchISD::REVB_2W", SDTUnaryOp>;
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//===----------------------------------------------------------------------===//
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// Operand and SDNode transformation definitions.
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@ -816,6 +818,19 @@ def : Pat<(loongarch_bstrpick GPR:$rj, uimm6:$msbd, uimm6:$lsbd),
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(BSTRPICK_D GPR:$rj, uimm6:$msbd, uimm6:$lsbd)>;
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} // Predicates = [IsLA64]
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/// Byte-swapping
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def : Pat<(loongarch_revb_2h GPR:$rj), (REVB_2H GPR:$rj)>;
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let Predicates = [IsLA32] in {
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def : Pat<(bswap GPR:$rj), (ROTRI_W (REVB_2H GPR:$rj), 16)>;
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} // Predicates = [IsLA32]
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let Predicates = [IsLA64] in {
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def : Pat<(loongarch_revb_2w GPR:$rj), (REVB_2W GPR:$rj)>;
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def : Pat<(bswap GPR:$rj), (REVB_D GPR:$rj)>;
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} // Predicates = [IsLA64]
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/// Loads
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multiclass LdPat<PatFrag LoadOp, LAInst Inst, ValueType vt = GRLenVT> {
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@ -0,0 +1,151 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=loongarch32 --verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix=LA32
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; RUN: llc -mtriple=loongarch64 --verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix=LA64
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declare i16 @llvm.bswap.i16(i16)
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declare i32 @llvm.bswap.i32(i32)
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declare i48 @llvm.bswap.i48(i48)
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declare i64 @llvm.bswap.i64(i64)
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declare i80 @llvm.bswap.i80(i80)
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declare i128 @llvm.bswap.i128(i128)
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define i16 @test_bswap_i16(i16 %a) nounwind {
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; LA32-LABEL: test_bswap_i16:
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; LA32: # %bb.0:
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; LA32-NEXT: revb.2h $a0, $a0
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; LA32-NEXT: jirl $zero, $ra, 0
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;
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; LA64-LABEL: test_bswap_i16:
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; LA64: # %bb.0:
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; LA64-NEXT: revb.2h $a0, $a0
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; LA64-NEXT: jirl $zero, $ra, 0
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%tmp = call i16 @llvm.bswap.i16(i16 %a)
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ret i16 %tmp
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}
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define i32 @test_bswap_i32(i32 %a) nounwind {
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; LA32-LABEL: test_bswap_i32:
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; LA32: # %bb.0:
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; LA32-NEXT: revb.2h $a0, $a0
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; LA32-NEXT: rotri.w $a0, $a0, 16
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; LA32-NEXT: jirl $zero, $ra, 0
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;
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; LA64-LABEL: test_bswap_i32:
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; LA64: # %bb.0:
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; LA64-NEXT: revb.2w $a0, $a0
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; LA64-NEXT: jirl $zero, $ra, 0
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%tmp = call i32 @llvm.bswap.i32(i32 %a)
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ret i32 %tmp
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}
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define i64 @test_bswap_i64(i64 %a) nounwind {
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; LA32-LABEL: test_bswap_i64:
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; LA32: # %bb.0:
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; LA32-NEXT: revb.2h $a1, $a1
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; LA32-NEXT: rotri.w $a2, $a1, 16
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; LA32-NEXT: revb.2h $a0, $a0
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; LA32-NEXT: rotri.w $a1, $a0, 16
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; LA32-NEXT: move $a0, $a2
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; LA32-NEXT: jirl $zero, $ra, 0
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;
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; LA64-LABEL: test_bswap_i64:
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; LA64: # %bb.0:
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; LA64-NEXT: revb.d $a0, $a0
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; LA64-NEXT: jirl $zero, $ra, 0
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%tmp = call i64 @llvm.bswap.i64(i64 %a)
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ret i64 %tmp
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}
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;; Bswap on non-native integer widths.
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define i48 @test_bswap_i48(i48 %a) nounwind {
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; LA32-LABEL: test_bswap_i48:
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; LA32: # %bb.0:
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; LA32-NEXT: revb.2h $a1, $a1
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; LA32-NEXT: rotri.w $a1, $a1, 16
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; LA32-NEXT: srli.w $a1, $a1, 16
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; LA32-NEXT: revb.2h $a0, $a0
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; LA32-NEXT: rotri.w $a2, $a0, 16
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; LA32-NEXT: slli.w $a0, $a2, 16
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; LA32-NEXT: or $a0, $a1, $a0
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; LA32-NEXT: srli.w $a1, $a2, 16
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; LA32-NEXT: jirl $zero, $ra, 0
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;
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; LA64-LABEL: test_bswap_i48:
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; LA64: # %bb.0:
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; LA64-NEXT: revb.d $a0, $a0
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; LA64-NEXT: srli.d $a0, $a0, 16
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; LA64-NEXT: jirl $zero, $ra, 0
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%tmp = call i48 @llvm.bswap.i48(i48 %a)
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ret i48 %tmp
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}
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define i80 @test_bswap_i80(i80 %a) nounwind {
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; LA32-LABEL: test_bswap_i80:
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; LA32: # %bb.0:
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; LA32-NEXT: ld.w $a2, $a1, 0
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; LA32-NEXT: revb.2h $a2, $a2
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; LA32-NEXT: rotri.w $a2, $a2, 16
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; LA32-NEXT: ld.w $a3, $a1, 4
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; LA32-NEXT: revb.2h $a3, $a3
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; LA32-NEXT: rotri.w $a3, $a3, 16
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; LA32-NEXT: srli.w $a4, $a3, 16
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; LA32-NEXT: slli.w $a5, $a2, 16
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; LA32-NEXT: or $a4, $a5, $a4
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; LA32-NEXT: srli.w $a2, $a2, 16
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; LA32-NEXT: st.h $a2, $a0, 8
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; LA32-NEXT: st.w $a4, $a0, 4
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; LA32-NEXT: slli.w $a2, $a3, 16
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; LA32-NEXT: ld.w $a1, $a1, 8
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; LA32-NEXT: revb.2h $a1, $a1
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; LA32-NEXT: rotri.w $a1, $a1, 16
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; LA32-NEXT: srli.w $a1, $a1, 16
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; LA32-NEXT: or $a1, $a1, $a2
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; LA32-NEXT: st.w $a1, $a0, 0
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; LA32-NEXT: jirl $zero, $ra, 0
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;
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; LA64-LABEL: test_bswap_i80:
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; LA64: # %bb.0:
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; LA64-NEXT: revb.d $a1, $a1
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; LA64-NEXT: srli.d $a1, $a1, 48
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; LA64-NEXT: revb.d $a2, $a0
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; LA64-NEXT: slli.d $a0, $a2, 16
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; LA64-NEXT: or $a0, $a1, $a0
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; LA64-NEXT: srli.d $a1, $a2, 48
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; LA64-NEXT: jirl $zero, $ra, 0
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%tmp = call i80 @llvm.bswap.i80(i80 %a)
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ret i80 %tmp
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}
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define i128 @test_bswap_i128(i128 %a) nounwind {
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; LA32-LABEL: test_bswap_i128:
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; LA32: # %bb.0:
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; LA32-NEXT: ld.w $a2, $a1, 0
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; LA32-NEXT: revb.2h $a2, $a2
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; LA32-NEXT: rotri.w $a2, $a2, 16
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; LA32-NEXT: st.w $a2, $a0, 12
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; LA32-NEXT: ld.w $a2, $a1, 4
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; LA32-NEXT: revb.2h $a2, $a2
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; LA32-NEXT: rotri.w $a2, $a2, 16
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; LA32-NEXT: st.w $a2, $a0, 8
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; LA32-NEXT: ld.w $a2, $a1, 8
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; LA32-NEXT: revb.2h $a2, $a2
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; LA32-NEXT: rotri.w $a2, $a2, 16
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; LA32-NEXT: st.w $a2, $a0, 4
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; LA32-NEXT: ld.w $a1, $a1, 12
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; LA32-NEXT: revb.2h $a1, $a1
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; LA32-NEXT: rotri.w $a1, $a1, 16
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; LA32-NEXT: st.w $a1, $a0, 0
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; LA32-NEXT: jirl $zero, $ra, 0
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;
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; LA64-LABEL: test_bswap_i128:
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; LA64: # %bb.0:
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; LA64-NEXT: revb.d $a2, $a1
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; LA64-NEXT: revb.d $a1, $a0
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; LA64-NEXT: move $a0, $a2
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; LA64-NEXT: jirl $zero, $ra, 0
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%tmp = call i128 @llvm.bswap.i128(i128 %a)
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ret i128 %tmp
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}
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