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[mips] Emit two CFI offset directives per double precision SDC1/LDC1 

instead of just one for FR=1 registers
Differential Revision: http://reviews.llvm.org/D4310

llvm-svn: 212769
This commit is contained in:
Zoran Jovanovic 2014-07-10 22:23:30 +00:00
parent 3c4780e8c3
commit f34b454219
4 changed files with 75 additions and 4 deletions
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9
llvm/lib/Target/Mips/MipsCallingConv.td
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@ -26,9 +26,9 @@ def RetCC_MipsO32 : CallingConv<[
// f32 are returned in registers F0, F2
CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
// f64 arguments are returned in D0_64 and D1_64 in FP64bit mode or
// f64 arguments are returned in D0_64 and D2_64 in FP64bit mode or
// in D0 and D1 in FP32bit mode.
CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D1_64]>>>,
CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D2_64]>>>,
CCIfType<[f64], CCIfSubtarget<"isNotFP64bit()", CCAssignToReg<[D0, D1]>>>
]>;
@ -247,8 +247,9 @@ def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
(sequence "S%u", 7, 0))>;
def CSR_O32_FP64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 20), RA, FP,
(sequence "S%u", 7, 0))>;
def CSR_O32_FP64 :
CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), RA, FP,
(sequence "S%u", 7, 0))>;
def CSR_N32 : CalleeSavedRegs<(add D20_64, D22_64, D24_64, D26_64, D28_64,
D30_64, RA_64, FP_64, GP_64,

16
llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
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@ -343,6 +343,22 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);
} else if (Mips::FGR64RegClass.contains(Reg)) {
unsigned Reg0 = MRI->getDwarfRegNum(Reg, true);
unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1;
if (!STI.isLittle())
std::swap(Reg0, Reg1);
unsigned CFIIndex = MMI.addFrameInst(
MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);
CFIIndex = MMI.addFrameInst(
MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);
} else {
// Reg is either in GPR32 or FGR32.
unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(

13
llvm/test/CodeGen/Mips/cconv/return-hard-float.ll
View File

@ -10,6 +10,9 @@
; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static -mattr=+o32,+fp64 < %s | FileCheck --check-prefix=ALL --check-prefix=032FP64 %s
; RUN: llc -mtriple=mipsel-linux-gnu -relocation-model=static -mattr=+o32,+fp64 < %s | FileCheck --check-prefix=ALL --check-prefix=032FP64 %s
; Test the float returns for all ABI's and byte orders as specified by
; section 5 of MD00305 (MIPS ABIs Described).
@ -44,3 +47,13 @@ entry:
; N32-DAG: ldc1 $f0, %lo(double)([[R1:\$[0-9]+]])
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(double)($1)
; N64-DAG: ldc1 $f0, 0([[R1]])
define { double, double } @retComplexDouble() #0 {
%retval = alloca { double, double }, align 8
%1 = load { double, double }* %retval
ret { double, double } %1
}
; ALL-LABEL: retComplexDouble:
; 032FP64-DAG: ldc1 $f0, 0($sp)
; 032FP64-DAG: ldc1 $f2, 8($sp)

41
llvm/test/CodeGen/Mips/cfi_offset.ll Normal file
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@ -0,0 +1,41 @@
; RUN: llc -march=mips -mattr=+o32 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-EB
; RUN: llc -march=mipsel -mattr=+o32 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-EL
; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-EB
; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-EL
; RUN: llc -march=mips -mattr=+o32,+fp64 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-EB
; RUN: llc -march=mipsel -mattr=+o32,+fp64 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-EL
@var = global double 0.0
declare void @foo(...)
define void @bar() {
; CHECK-LABEL: bar:
; CHECK: .cfi_def_cfa_offset 40
; CHECK: sdc1 $f22, 32($sp)
; CHECK: sdc1 $f20, 24($sp)
; CHECK: sw $ra, 20($sp)
; CHECK: sw $16, 16($sp)
; CHECK-EB: .cfi_offset 55, -8
; CHECK-EB: .cfi_offset 54, -4
; CHECK-EB: .cfi_offset 53, -16
; CHECK-EB: .cfi_offset 52, -12
; CHECK-EL: .cfi_offset 54, -8
; CHECK-EL: .cfi_offset 55, -4
; CHECK-EL: .cfi_offset 52, -16
; CHECK-EL: .cfi_offset 53, -12
; CHECK: .cfi_offset 31, -20
; CHECK: .cfi_offset 16, -24
%val1 = load volatile double* @var
%val2 = load volatile double* @var
call void (...)* @foo() nounwind
store volatile double %val1, double* @var
store volatile double %val2, double* @var
ret void
}