forked from OSchip/llvm-project
[AArch64] Expand vector SDIVREM/UDIVREM operations.
http://reviews.llvm.org/D15214 Patch by Ana Pazos <apazos@codeaurora.org>! llvm-svn: 254773
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@ -237,6 +237,10 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
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setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
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for (MVT VT : MVT::vector_valuetypes()) {
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setOperationAction(ISD::SDIVREM, VT, Expand);
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setOperationAction(ISD::UDIVREM, VT, Expand);
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}
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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setOperationAction(ISD::SREM, MVT::i64, Expand);
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setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
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@ -0,0 +1,22 @@
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; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -mattr=+neon | FileCheck %s
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; SDIVREM/UDIVREM DAG nodes are generated but expanded when lowering and
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; should not generate select error.
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define <2 x i32> @test_udivrem(<2 x i32> %x, < 2 x i32> %y, < 2 x i32>* %z) {
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; CHECK-LABEL: test_udivrem
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; CHECK-DAG: udivrem
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; CHECK-NOT: LLVM ERROR: Cannot select
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%div = udiv <2 x i32> %x, %y
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store <2 x i32> %div, <2 x i32>* %z
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%1 = urem <2 x i32> %x, %y
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ret <2 x i32> %1
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}
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define <4 x i32> @test_sdivrem(<4 x i32> %x, <4 x i32>* %y) {
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; CHECK-LABEL: test_sdivrem
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; CHECK-DAG: sdivrem
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%div = sdiv <4 x i32> %x, < i32 20, i32 20, i32 20, i32 20 >
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store <4 x i32> %div, <4 x i32>* %y
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%1 = srem <4 x i32> %x, < i32 20, i32 20, i32 20, i32 20 >
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ret <4 x i32> %1
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}
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