forked from OSchip/llvm-project
Add a target hook to add pre- post-regalloc scheduling passes.
llvm-svn: 83144
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3ea1ba7739
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@ -362,20 +362,28 @@ public:
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return true;
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}
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/// addPreRegAllocPasses - This method may be implemented by targets that want
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/// to run passes immediately before register allocation. This should return
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/// addPreRegAlloc - This method may be implemented by targets that want to
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/// run passes immediately before register allocation. This should return
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/// true if -print-machineinstrs should print after these passes.
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virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
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return false;
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}
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/// addPostRegAllocPasses - This method may be implemented by targets that
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/// want to run passes after register allocation but before prolog-epilog
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/// addPostRegAlloc - This method may be implemented by targets that want
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/// to run passes after register allocation but before prolog-epilog
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/// insertion. This should return true if -print-machineinstrs should print
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/// after these passes.
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virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
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return false;
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}
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/// addPreSched2 - This method may be implemented by targets that want to
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/// run passes after prolog-epilog insertion and before the second instruction
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/// scheduling pass. This should return true if -print-machineinstrs should
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/// print after these passes.
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virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
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return false;
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}
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/// addPreEmitPass - This pass may be implemented by targets that want to run
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/// passes immediately before machine code is emitted. This should return
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@ -317,6 +317,10 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
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PM.add(createPrologEpilogCodeInserter());
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printAndVerify(PM);
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// Run pre-sched2 passes.
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if (addPreSched2(PM, OptLevel))
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printAndVerify(PM);
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// Second pass scheduler.
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if (OptLevel != CodeGenOpt::None) {
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PM.add(createPostRAScheduler());
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