forked from OSchip/llvm-project
Revert r291640 change to fold X86 comparison with atomic_load_add.
Even with the fix from r291630, this still causes problems. I get widespread assertion failures in the Swift runtime's WeakRefCount::increment() function. I sent a reduced testcase in reply to the commit. llvm-svn: 292242
This commit is contained in:
Bob Wilson
parent
b6e32daa81
commit
f2d0b68b3b
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@ -29515,19 +29515,11 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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/// Combine brcond/cmov/setcc/.. based on comparing the result of
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/// atomic_load_add to use EFLAGS produced by the addition
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/// directly if possible. For example:
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///
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/// (setcc (cmp (atomic_load_add x, -C) C), COND_E)
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/// becomes:
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/// (setcc (LADD x, -C), COND_E)
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///
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/// and
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/// Combine:
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/// (brcond/cmov/setcc .., (cmp (atomic_load_add x, 1), 0), COND_S)
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/// becomes:
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/// to:
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/// (brcond/cmov/setcc .., (LADD x, 1), COND_LE)
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///
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/// i.e., reusing the EFLAGS produced by the LOCKed instruction.
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/// Note that this is only legal for some op/cc combinations.
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static SDValue combineSetCCAtomicArith(SDValue Cmp, X86::CondCode &CC,
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SelectionDAG &DAG) {
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@ -29542,7 +29534,7 @@ static SDValue combineSetCCAtomicArith(SDValue Cmp, X86::CondCode &CC,
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if (!Cmp.hasOneUse())
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return SDValue();
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// This applies to variations of the common case:
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// This only applies to variations of the common case:
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// (icmp slt x, 0) -> (icmp sle (add x, 1), 0)
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// (icmp sge x, 0) -> (icmp sgt (add x, 1), 0)
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// (icmp sle x, 0) -> (icmp slt (sub x, 1), 0)
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@ -29561,9 +29553,8 @@ static SDValue combineSetCCAtomicArith(SDValue Cmp, X86::CondCode &CC,
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return SDValue();
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auto *CmpRHSC = dyn_cast<ConstantSDNode>(CmpRHS);
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if (!CmpRHSC)
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if (!CmpRHSC || CmpRHSC->getZExtValue() != 0)
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return SDValue();
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APInt Comparand = CmpRHSC->getAPIntValue();
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const unsigned Opc = CmpLHS.getOpcode();
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@ -29579,19 +29570,16 @@ static SDValue combineSetCCAtomicArith(SDValue Cmp, X86::CondCode &CC,
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if (Opc == ISD::ATOMIC_LOAD_SUB)
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Addend = -Addend;
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if (Comparand == -Addend) {
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// No change to CC.
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} else if (CC == X86::COND_S && Comparand == 0 && Addend == 1) {
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if (CC == X86::COND_S && Addend == 1)
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CC = X86::COND_LE;
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} else if (CC == X86::COND_NS && Comparand == 0 && Addend == 1) {
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else if (CC == X86::COND_NS && Addend == 1)
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CC = X86::COND_G;
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} else if (CC == X86::COND_G && Comparand == 0 && Addend == -1) {
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else if (CC == X86::COND_G && Addend == -1)
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CC = X86::COND_GE;
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} else if (CC == X86::COND_LE && Comparand == 0 && Addend == -1) {
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else if (CC == X86::COND_LE && Addend == -1)
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CC = X86::COND_L;
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} else {
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else
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return SDValue();
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}
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SDValue LockOp = lowerAtomicArithWithLOCK(CmpLHS, DAG);
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DAG.ReplaceAllUsesOfValueWith(CmpLHS.getValue(0),
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@ -192,68 +192,4 @@ entry:
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ret i8 %s2
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}
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define i8 @test_sub_1_setcc_eq(i64* %p) #0 {
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; CHECK-LABEL: test_sub_1_setcc_eq:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: lock decq (%rdi)
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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entry:
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%tmp0 = atomicrmw sub i64* %p, i64 1 seq_cst
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%tmp1 = icmp eq i64 %tmp0, 1
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%tmp2 = zext i1 %tmp1 to i8
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ret i8 %tmp2
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}
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define i8 @test_add_5_setcc_ne(i64* %p) #0 {
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; CHECK-LABEL: test_add_5_setcc_ne:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: lock addq $5, (%rdi)
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; CHECK-NEXT: setne %al
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; CHECK-NEXT: retq
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entry:
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%tmp0 = atomicrmw add i64* %p, i64 5 seq_cst
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%tmp1 = icmp ne i64 %tmp0, -5
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%tmp2 = zext i1 %tmp1 to i8
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ret i8 %tmp2
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}
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define i8 @test_add_5_setcc_ne_comparand_mismatch(i64* %p) #0 {
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; CHECK-LABEL: test_add_5_setcc_ne_comparand_mismatch:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: movl $5, %eax
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; CHECK-NEXT: lock xaddq %rax, (%rdi)
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; CHECK-NEXT: testq %rax, %rax
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; CHECK-NEXT: setne %al
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; CHECK-NEXT: retq
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entry:
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%tmp0 = atomicrmw add i64* %p, i64 5 seq_cst
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%tmp1 = icmp ne i64 %tmp0, 0
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%tmp2 = zext i1 %tmp1 to i8
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ret i8 %tmp2
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}
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declare void @g()
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define zeroext i1 @test_sub_1_setcc_jcc(i64* %p) local_unnamed_addr #0 {
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; TODO: It's possible to use "lock dec" here, but both uses of the cmp need to
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; be updated.
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; CHECK-LABEL: test_sub_1_setcc_jcc:
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; CHECK: # BB#0: # %entry
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; CHECK: movq $-1, %rax
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; CHECK-NEXT: lock xaddq %rax, (%rdi)
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; CHECK-NEXT: cmpq $1, %rax
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; CHECK-NEXT: sete %bl
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; CHECK-NEXT: jne
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entry:
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%add = atomicrmw volatile add i64* %p, i64 -1 seq_cst
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%cmp = icmp ne i64 %add, 1
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%not = xor i1 %cmp, true
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br i1 %cmp, label %else, label %then
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then:
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tail call void @g()
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br label %else
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else:
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ret i1 %not
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}
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attributes #0 = { nounwind }
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