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AMDGPU : Update TrapCode based on Trap Handler ABI. 

Differential Revision: http://reviews.llvm.org/D30232

llvm-svn: 295904
This commit is contained in:
Wei Ding 2017-02-22 23:22:19 +00:00
parent f9a28a287c
commit f2cce02eb2
5 changed files with 19 additions and 15 deletions
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16
llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
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@ -74,15 +74,19 @@ public:
TrapHandlerAbiHsa = 1 TrapHandlerAbiHsa = 1
}; };
enum TrapCode { enum TrapID {
TrapCodeBreakPoint = 0, TrapIDHardwareReserved = 0,
TrapCodeLLVMTrap = 1, TrapIDHSADebugTrap = 1,
TrapCodeLLVMDebugTrap = 2, TrapIDLLVMTrap = 2,
TrapCodeHSADebugTrap = 3 TrapIDLLVMDebugTrap = 3,
TrapIDDebugBreakpoint = 7,
TrapIDDebugReserved8 = 8,
TrapIDDebugReservedFE = 0xfe,
TrapIDDebugReservedFF = 0xff
}; };
enum TrapRegValues { enum TrapRegValues {
TrapCodeLLVMTrapRegValue = 1 LLVMTrapHandlerRegValue = 1
}; };
protected: protected:

4
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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@ -1804,10 +1804,10 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
.addReg(AMDGPU::SGPR0_SGPR1, RegState::Implicit); .addReg(AMDGPU::SGPR0_SGPR1, RegState::Implicit);
} else { } else {
switch (TrapType) { switch (TrapType) {
case SISubtarget::TrapCodeLLVMTrap: case SISubtarget::TrapIDLLVMTrap:
BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_ENDPGM)); BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_ENDPGM));
break; break;
case SISubtarget::TrapCodeLLVMDebugTrap: { case SISubtarget::TrapIDLLVMDebugTrap: {
DiagnosticInfoUnsupported NoTrap(*MF->getFunction(), DiagnosticInfoUnsupported NoTrap(*MF->getFunction(),
"debugtrap handler not supported", "debugtrap handler not supported",
DL, DL,

6
llvm/lib/Target/AMDGPU/SIInstrInfo.td
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@ -632,9 +632,9 @@ def DSTOMOD {
int NONE = 0; int NONE = 0;
} }
def TRAPTYPE { def TRAPID{
int LLVM_TRAP = 1; int LLVM_TRAP = 2;
int LLVM_DEBUG_TRAP = 2; int LLVM_DEBUG_TRAP = 3;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

4
llvm/lib/Target/AMDGPU/SIInstructions.td
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@ -391,12 +391,12 @@ def SI_PC_ADD_REL_OFFSET : SPseudoInstSI <
let Predicates = [isGCN] in { let Predicates = [isGCN] in {
def : Pat< def : Pat<
(trap), (trap),
(S_TRAP_PSEUDO TRAPTYPE.LLVM_TRAP) (S_TRAP_PSEUDO TRAPID.LLVM_TRAP)
>; >;
def : Pat< def : Pat<
(debugtrap), (debugtrap),
(S_TRAP_PSEUDO TRAPTYPE.LLVM_DEBUG_TRAP) (S_TRAP_PSEUDO TRAPID.LLVM_DEBUG_TRAP)
>; >;
def : Pat< def : Pat<

4
llvm/test/CodeGen/AMDGPU/trap.ll
View File

@ -28,7 +28,7 @@ declare void @llvm.debugtrap() #0
; GCN-LABEL: {{^}}hsa_trap: ; GCN-LABEL: {{^}}hsa_trap:
; HSA-TRAP: enable_trap_handler = 1 ; HSA-TRAP: enable_trap_handler = 1
; HSA-TRAP: s_mov_b64 s[0:1], s[4:5] ; HSA-TRAP: s_mov_b64 s[0:1], s[4:5]
; HSA-TRAP: s_trap 1 ; HSA-TRAP: s_trap 2
; for llvm.trap in hsa path without ABI, direct generate s_endpgm instruction without any warning information ; for llvm.trap in hsa path without ABI, direct generate s_endpgm instruction without any warning information
; NO-HSA-TRAP: enable_trap_handler = 0 ; NO-HSA-TRAP: enable_trap_handler = 0
@ -55,7 +55,7 @@ define void @hsa_trap() {
; GCN-LABEL: {{^}}hsa_debugtrap: ; GCN-LABEL: {{^}}hsa_debugtrap:
; HSA-TRAP: enable_trap_handler = 1 ; HSA-TRAP: enable_trap_handler = 1
; HSA-TRAP: s_mov_b64 s[0:1], s[4:5] ; HSA-TRAP: s_mov_b64 s[0:1], s[4:5]
; HSA-TRAP: s_trap 2 ; HSA-TRAP: s_trap 3
; for llvm.debugtrap in non-hsa path without ABI, generate a warning and a s_endpgm instruction ; for llvm.debugtrap in non-hsa path without ABI, generate a warning and a s_endpgm instruction
; NO-HSA-TRAP: enable_trap_handler = 0 ; NO-HSA-TRAP: enable_trap_handler = 0