forked from OSchip/llvm-project
[PowerPC] Turn on CR-Logical reducer pass
This re-commits r375152 which was pulled in r375233 because it broke the EXPENSIVE_CHECKS bot on Windows. The reason for the failure was a bug in the pass that the commit turned on by default. This patch fixes that bug and turns the pass back on. This patch has been verified on the buildbot that originally failed thanks to Simon Pilgrim. Differential revision: https://reviews.llvm.org/D52431 llvm-svn: 375497
This commit is contained in:
Nemanja Ivanovic
parent
8e050e41a4
commit
f2c8f3b181
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@ -381,10 +381,10 @@ private:
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const MachineBranchProbabilityInfo *MBPI;
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// A vector to contain all the CR logical operations
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std::vector<CRLogicalOpInfo> AllCRLogicalOps;
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SmallVector<CRLogicalOpInfo, 16> AllCRLogicalOps;
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void initialize(MachineFunction &MFParm);
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void collectCRLogicals();
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bool handleCROp(CRLogicalOpInfo &CRI);
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bool handleCROp(unsigned Idx);
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bool splitBlockOnBinaryCROp(CRLogicalOpInfo &CRI);
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static bool isCRLogical(MachineInstr &MI) {
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unsigned Opc = MI.getOpcode();
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@ -398,7 +398,7 @@ private:
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// Not using a range-based for loop here as the vector may grow while being
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// operated on.
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for (unsigned i = 0; i < AllCRLogicalOps.size(); i++)
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Changed |= handleCROp(AllCRLogicalOps[i]);
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Changed |= handleCROp(i);
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return Changed;
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}
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@ -578,10 +578,11 @@ void PPCReduceCRLogicals::initialize(MachineFunction &MFParam) {
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/// a unary CR logical might be used to change the condition code on a
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/// comparison feeding it. A nullary CR logical might simply be removable
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/// if the user of the bit it [un]sets can be transformed.
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bool PPCReduceCRLogicals::handleCROp(CRLogicalOpInfo &CRI) {
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bool PPCReduceCRLogicals::handleCROp(unsigned Idx) {
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// We can definitely split a block on the inputs to a binary CR operation
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// whose defs and (single) use are within the same block.
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bool Changed = false;
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CRLogicalOpInfo CRI = AllCRLogicalOps[Idx];
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if (CRI.IsBinary && CRI.ContainedInBlock && CRI.SingleUse && CRI.FeedsBR &&
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CRI.DefsSingleUse) {
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Changed = splitBlockOnBinaryCROp(CRI);
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@ -93,7 +93,7 @@ EnableMachineCombinerPass("ppc-machine-combiner",
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static cl::opt<bool>
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ReduceCRLogical("ppc-reduce-cr-logicals",
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cl::desc("Expand eligible cr-logical binary ops to branches"),
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cl::init(false), cl::Hidden);
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cl::init(true), cl::Hidden);
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extern "C" void LLVMInitializePowerPCTarget() {
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// Register the targets
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RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());
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@ -36,7 +36,7 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
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; CHECK-NEXT: # %bb.1: # %bb5
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 0
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; CHECK-NEXT: b .LBB0_16
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; CHECK-NEXT: b .LBB0_17
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; CHECK-NEXT: .LBB0_2: # %bb1
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; CHECK-NEXT: lfd 0, 400(1)
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; CHECK-NEXT: lis 3, 15856
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@ -166,13 +166,11 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
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; CHECK-NEXT: bl __gcc_qsub@PLT
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; CHECK-NEXT: stfd 2, 176(1)
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; CHECK-NEXT: stfd 1, 168(1)
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; CHECK-NEXT: fcmpu 0, 2, 27
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; CHECK-NEXT: fcmpu 1, 2, 27
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; CHECK-NEXT: lwz 3, 180(1)
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; CHECK-NEXT: fcmpu 1, 1, 27
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; CHECK-NEXT: crandc 20, 6, 0
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; CHECK-NEXT: cror 21, 5, 7
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; CHECK-NEXT: fcmpu 0, 1, 27
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; CHECK-NEXT: crandc 20, 2, 4
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; CHECK-NEXT: stw 3, 268(1)
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; CHECK-NEXT: cror 20, 21, 20
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; CHECK-NEXT: lwz 3, 176(1)
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; CHECK-NEXT: stw 3, 264(1)
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; CHECK-NEXT: lwz 3, 172(1)
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@ -181,8 +179,11 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
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; CHECK-NEXT: lwz 3, 168(1)
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; CHECK-NEXT: stw 3, 272(1)
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; CHECK-NEXT: lfd 31, 272(1)
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; CHECK-NEXT: bc 12, 20, .LBB0_13
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; CHECK-NEXT: # %bb.10: # %bb2
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; CHECK-NEXT: bc 12, 20, .LBB0_14
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; CHECK-NEXT: # %bb.10: # %bb1
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; CHECK-NEXT: cror 20, 1, 3
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; CHECK-NEXT: bc 12, 20, .LBB0_14
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; CHECK-NEXT: # %bb.11: # %bb2
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; CHECK-NEXT: fneg 28, 31
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; CHECK-NEXT: stfd 28, 48(1)
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; CHECK-NEXT: lis 3, 16864
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@ -231,15 +232,15 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
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; CHECK-NEXT: crandc 20, 6, 1
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; CHECK-NEXT: cror 20, 4, 20
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; CHECK-NEXT: addis 3, 3, -32768
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; CHECK-NEXT: bc 12, 20, .LBB0_12
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; CHECK-NEXT: # %bb.11: # %bb2
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; CHECK-NEXT: bc 12, 20, .LBB0_13
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; CHECK-NEXT: # %bb.12: # %bb2
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; CHECK-NEXT: ori 3, 4, 0
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; CHECK-NEXT: b .LBB0_12
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; CHECK-NEXT: .LBB0_12: # %bb2
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; CHECK-NEXT: b .LBB0_13
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; CHECK-NEXT: .LBB0_13: # %bb2
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; CHECK-NEXT: subfic 4, 3, 0
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; CHECK-NEXT: subfe 3, 29, 30
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; CHECK-NEXT: b .LBB0_16
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; CHECK-NEXT: .LBB0_13: # %bb3
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; CHECK-NEXT: b .LBB0_17
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; CHECK-NEXT: .LBB0_14: # %bb3
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; CHECK-NEXT: stfd 31, 112(1)
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: stw 3, 148(1)
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@ -286,13 +287,13 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
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; CHECK-NEXT: crandc 20, 6, 0
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; CHECK-NEXT: cror 20, 5, 20
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; CHECK-NEXT: addis 3, 3, -32768
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; CHECK-NEXT: bc 12, 20, .LBB0_14
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; CHECK-NEXT: b .LBB0_15
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; CHECK-NEXT: .LBB0_14: # %bb3
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; CHECK-NEXT: addi 4, 3, 0
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; CHECK-NEXT: bc 12, 20, .LBB0_15
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; CHECK-NEXT: b .LBB0_16
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; CHECK-NEXT: .LBB0_15: # %bb3
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; CHECK-NEXT: addi 4, 3, 0
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; CHECK-NEXT: .LBB0_16: # %bb3
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; CHECK-NEXT: mr 3, 30
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; CHECK-NEXT: .LBB0_16: # %bb5
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; CHECK-NEXT: .LBB0_17: # %bb5
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; CHECK-NEXT: lfd 31, 456(1) # 8-byte Folded Reload
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; CHECK-NEXT: lfd 30, 448(1) # 8-byte Folded Reload
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; CHECK-NEXT: lfd 29, 440(1) # 8-byte Folded Reload
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@ -1,5 +1,7 @@
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
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; RUN: -ppc-reduce-cr-logicals=false < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
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; RUN: -ppc-reduce-cr-logicals=false < %s | FileCheck %s
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define signext i32 @testi32slt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
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; CHECK-LABEL: testi32slt
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@ -14,13 +14,15 @@ define void @f(i8*, i8*, i64*) {
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; CHECK-NEXT: li 4, 0
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; CHECK-NEXT: .p2align 5
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; CHECK-NEXT: .LBB0_2: #
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; CHECK-NEXT: cmplwi 4, 14
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; CHECK-NEXT: cmpd 1, 3, 4
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; CHECK-NEXT: sldi 6, 6, 4
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; CHECK-NEXT: cror 20, 6, 1
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; CHECK-NEXT: addi 4, 4, 1
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; CHECK-NEXT: bc 4, 20, .LBB0_2
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; CHECK-NEXT: # %bb.3:
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; CHECK-NEXT: cmplwi 4, 14
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; CHECK-NEXT: addi 7, 4, 1
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; CHECK-NEXT: bc 12, 1, .LBB0_4
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; CHECK-NEXT: # %bb.3: #
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; CHECK-NEXT: cmpd 3, 4
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; CHECK-NEXT: mr 4, 7
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; CHECK-NEXT: bc 4, 2, .LBB0_2
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; CHECK-NEXT: .LBB0_4:
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; CHECK-NEXT: std 6, 8(5)
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; CHECK-NEXT: blr
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@ -16,16 +16,17 @@ define dso_local void @test(void (i32)* nocapture %fp, i32 signext %Arg, i32 sig
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; CHECK-NEXT: std r0, 16(r1)
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; CHECK-NEXT: stdu r1, -64(r1)
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; CHECK-NEXT: mr r29, r5
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; CHECK-NEXT: cmpwi cr1, r4, 11
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; CHECK-NEXT: mr r30, r3
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; CHECK-NEXT: extsw r28, r4
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; CHECK-NEXT: std r2, 24(r1)
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; CHECK-NEXT: cmpwi r29, 1
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; CHECK-NEXT: cror 4*cr5+lt, lt, 4*cr1+lt
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; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_2
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; CHECK-NEXT: bc 12, lt, .LBB0_3
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; CHECK-NEXT: # %bb.1: # %entry
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; CHECK-NEXT: cmpwi cr0, r4, 11
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; CHECK-NEXT: bc 12, lt, .LBB0_3
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; CHECK-NEXT: .p2align 5
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; CHECK-NEXT: .LBB0_1: # %for.body.us
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: .LBB0_2: # %for.body.us
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; CHECK-NEXT: #
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; CHECK-NEXT: mtctr r30
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; CHECK-NEXT: mr r3, r28
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; CHECK-NEXT: mr r12, r30
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@ -33,8 +34,8 @@ define dso_local void @test(void (i32)* nocapture %fp, i32 signext %Arg, i32 sig
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; CHECK-NEXT: ld 2, 24(r1)
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; CHECK-NEXT: addi r29, r29, -1
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; CHECK-NEXT: cmplwi r29, 0
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; CHECK-NEXT: bne cr0, .LBB0_1
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; CHECK-NEXT: .LBB0_2: # %for.cond.cleanup
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; CHECK-NEXT: bne cr0, .LBB0_2
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; CHECK-NEXT: .LBB0_3: # %for.cond.cleanup
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; CHECK-NEXT: mtctr r30
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; CHECK-NEXT: mr r3, r28
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; CHECK-NEXT: mr r12, r30
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@ -240,22 +240,23 @@ entry:
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define i128 @invalidv1i128(<2 x i128> %v1, <2 x i128> %v2) {
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; CHECK-LABEL: invalidv1i128:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mfvsrd 3, 36
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; CHECK-NEXT: xxswapd 0, 36
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; CHECK-NEXT: mfvsrd 4, 36
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; CHECK-NEXT: mfvsrd 5, 34
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; CHECK-NEXT: mfvsrd 4, 34
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; CHECK-NEXT: xxswapd 1, 34
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; CHECK-NEXT: cmpld 4, 3
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; CHECK-NEXT: cmpd 1, 4, 3
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; CHECK-NEXT: mfvsrd 3, 0
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; CHECK-NEXT: xxswapd 0, 34
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; CHECK-NEXT: cmpld 5, 4
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; CHECK-NEXT: cmpd 1, 5, 4
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; CHECK-NEXT: crandc 20, 4, 2
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; CHECK-NEXT: mfvsrd 6, 0
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; CHECK-NEXT: cmpld 1, 6, 3
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; CHECK-NEXT: crand 21, 2, 4
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; CHECK-NEXT: cror 20, 21, 20
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; CHECK-NEXT: bc 12, 20, .LBB12_2
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; CHECK-NEXT: mfvsrd 4, 1
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; CHECK-NEXT: cmpld 1, 4, 3
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; CHECK-NEXT: bc 12, 20, .LBB12_3
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: crand 20, 2, 4
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; CHECK-NEXT: bc 12, 20, .LBB12_3
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; CHECK-NEXT: # %bb.2:
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; CHECK-NEXT: vmr 2, 4
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; CHECK-NEXT: .LBB12_2:
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; CHECK-NEXT: .LBB12_3:
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; CHECK-NEXT: xxswapd 0, 34
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; CHECK-NEXT: mfvsrd 4, 34
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; CHECK-NEXT: mfvsrd 3, 0
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