forked from OSchip/llvm-project
AMDGPU/SI: add llvm.amdgcn.image.load/store[.mip] intrinsics
Summary: These correspond to IMAGE_LOAD/STORE[_MIP] and are going to be used by Mesa for the GL_ARB_shader_image_load_store extension. IMAGE_LOAD is already matched by llvm.SI.image.load. That intrinsic has a legacy name and pretends not to read memory. Differential Revision: http://reviews.llvm.org/D17276 llvm-svn: 261224
This commit is contained in:
Nicolai Haehnle
parent
7a545536f5
commit
f2c64db55a
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@ -143,6 +143,35 @@ def int_amdgcn_cubetc : GCCBuiltin<"__builtin_amdgcn_cubetc">,
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[llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]
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>;
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class AMDGPUImageLoad : Intrinsic <
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[llvm_v4f32_ty], // vdata(VGPR)
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[llvm_anyint_ty, // vaddr(VGPR)
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llvm_v8i32_ty, // rsrc(SGPR)
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llvm_i32_ty, // dmask(imm)
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llvm_i1_ty, // r128(imm)
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llvm_i1_ty, // da(imm)
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llvm_i1_ty, // glc(imm)
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llvm_i1_ty], // slc(imm)
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[IntrReadMem]>;
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def int_amdgcn_image_load : AMDGPUImageLoad;
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def int_amdgcn_image_load_mip : AMDGPUImageLoad;
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class AMDGPUImageStore : Intrinsic <
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[],
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[llvm_v4f32_ty, // vdata(VGPR)
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llvm_anyint_ty, // vaddr(VGPR)
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llvm_v8i32_ty, // rsrc(SGPR)
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llvm_i32_ty, // dmask(imm)
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llvm_i1_ty, // r128(imm)
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llvm_i1_ty, // da(imm)
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llvm_i1_ty, // glc(imm)
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llvm_i1_ty], // slc(imm)
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[]>;
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def int_amdgcn_image_store : AMDGPUImageStore;
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def int_amdgcn_image_store_mip : AMDGPUImageStore;
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def int_amdgcn_read_workdim : AMDGPUReadPreloadRegisterIntrinsic <
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"__builtin_amdgcn_read_workdim">;
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@ -2766,12 +2766,13 @@ SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
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SelectionDAG &DAG) const {
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const SIInstrInfo *TII =
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static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
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unsigned Opcode = Node->getMachineOpcode();
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if (TII->isMIMG(Node->getMachineOpcode()))
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if (TII->isMIMG(Opcode) && !TII->get(Opcode).mayStore())
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adjustWritemask(Node, DAG);
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if (Node->getMachineOpcode() == AMDGPU::INSERT_SUBREG ||
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Node->getMachineOpcode() == AMDGPU::REG_SEQUENCE) {
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if (Opcode == AMDGPU::INSERT_SUBREG ||
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Opcode == AMDGPU::REG_SEQUENCE) {
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legalizeTargetIndependentNode(Node, DAG);
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return Node;
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}
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@ -2905,12 +2905,12 @@ class MIMG_Helper <bits<7> op, dag outs, dag ins, string asm,
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class MIMG_NoSampler_Helper <bits<7> op, string asm,
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RegisterClass dst_rc,
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RegisterClass src_rc,
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RegisterClass addr_rc,
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string dns=""> : MIMG_Helper <
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op,
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(outs dst_rc:$vdata),
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(ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
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i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
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i1imm:$tfe, i1imm:$lwe, i1imm:$slc, addr_rc:$vaddr,
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SReg_256:$srsrc),
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asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
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#" $tfe, $lwe, $slc, $vaddr, $srsrc",
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@ -2937,6 +2937,41 @@ multiclass MIMG_NoSampler <bits<7> op, string asm> {
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defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
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}
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class MIMG_Store_Helper <bits<7> op, string asm,
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RegisterClass data_rc,
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RegisterClass addr_rc> : MIMG_Helper <
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op,
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(outs),
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(ins data_rc:$vdata, i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
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i1imm:$tfe, i1imm:$lwe, i1imm:$slc, addr_rc:$vaddr,
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SReg_256:$srsrc),
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asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
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#" $tfe, $lwe, $slc, $vaddr, $srsrc"> {
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let ssamp = 0;
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let mayLoad = 1; // TableGen requires this for matching with the intrinsics
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let mayStore = 1;
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let hasSideEffects = 1;
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let hasPostISelHook = 0;
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}
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multiclass MIMG_Store_Addr_Helper <bits<7> op, string asm,
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RegisterClass data_rc,
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int channels> {
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def _V1 : MIMG_Store_Helper <op, asm, data_rc, VGPR_32>,
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MIMG_Mask<asm#"_V1", channels>;
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def _V2 : MIMG_Store_Helper <op, asm, data_rc, VReg_64>,
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MIMG_Mask<asm#"_V2", channels>;
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def _V4 : MIMG_Store_Helper <op, asm, data_rc, VReg_128>,
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MIMG_Mask<asm#"_V4", channels>;
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}
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multiclass MIMG_Store <bits<7> op, string asm> {
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defm _V1 : MIMG_Store_Addr_Helper <op, asm, VGPR_32, 1>;
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defm _V2 : MIMG_Store_Addr_Helper <op, asm, VReg_64, 2>;
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defm _V3 : MIMG_Store_Addr_Helper <op, asm, VReg_96, 3>;
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defm _V4 : MIMG_Store_Addr_Helper <op, asm, VReg_128, 4>;
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}
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class MIMG_Sampler_Helper <bits<7> op, string asm,
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RegisterClass dst_rc,
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RegisterClass src_rc,
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@ -1063,8 +1063,8 @@ defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "image_load_mip">;
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//def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"image_load_pck_sgn", 0x00000003>;
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//def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"image_load_mip_pck", 0x00000004>;
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//def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"image_load_mip_pck_sgn", 0x00000005>;
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//def IMAGE_STORE : MIMG_NoPattern_ <"image_store", 0x00000008>;
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//def IMAGE_STORE_MIP : MIMG_NoPattern_ <"image_store_mip", 0x00000009>;
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defm IMAGE_STORE : MIMG_Store <0x00000008, "image_store">;
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defm IMAGE_STORE_MIP : MIMG_Store <0x00000009, "image_store_mip">;
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//def IMAGE_STORE_PCK : MIMG_NoPattern_ <"image_store_pck", 0x0000000a>;
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//def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"image_store_mip_pck", 0x0000000b>;
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defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "image_get_resinfo">;
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@ -2230,8 +2230,8 @@ multiclass SampleRawPatterns<SDPatternOperator name, string opcode> {
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// Image only
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class ImagePattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
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(name vt:$addr, v8i32:$rsrc, i32:$dmask, i32:$unorm,
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i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe),
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(name vt:$addr, v8i32:$rsrc, imm:$dmask, imm:$unorm,
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imm:$r128, imm:$da, imm:$glc, imm:$slc, imm:$tfe, imm:$lwe),
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(opcode (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $da),
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(as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $slc),
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$addr, $rsrc)
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@ -2243,6 +2243,32 @@ multiclass ImagePatterns<SDPatternOperator name, string opcode> {
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def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
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}
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class ImageLoadPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
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(name vt:$addr, v8i32:$rsrc, imm:$dmask, imm:$r128, imm:$da, imm:$glc,
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imm:$slc),
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(opcode (as_i32imm $dmask), 1, (as_i1imm $glc), (as_i1imm $da),
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(as_i1imm $r128), 0, 0, (as_i1imm $slc), $addr, $rsrc)
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>;
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multiclass ImageLoadPatterns<SDPatternOperator name, string opcode> {
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def : ImageLoadPattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
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def : ImageLoadPattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
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def : ImageLoadPattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
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}
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class ImageStorePattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
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(name v4f32:$data, vt:$addr, v8i32:$rsrc, i32:$dmask, imm:$r128, imm:$da,
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imm:$glc, imm:$slc),
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(opcode $data, (as_i32imm $dmask), 1, (as_i1imm $glc), (as_i1imm $da),
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(as_i1imm $r128), 0, 0, (as_i1imm $slc), $addr, $rsrc)
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>;
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multiclass ImageStorePatterns<SDPatternOperator name, string opcode> {
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def : ImageStorePattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
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def : ImageStorePattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
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def : ImageStorePattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
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}
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// Basic sample
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defm : SampleRawPatterns<int_SI_image_sample, "IMAGE_SAMPLE">;
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defm : SampleRawPatterns<int_SI_image_sample_cl, "IMAGE_SAMPLE_CL">;
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@ -2339,6 +2365,10 @@ def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V4, v4i32>;
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def : ImagePattern<int_SI_getresinfo, IMAGE_GET_RESINFO_V4_V1, i32>;
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defm : ImagePatterns<int_SI_image_load, "IMAGE_LOAD">;
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defm : ImagePatterns<int_SI_image_load_mip, "IMAGE_LOAD_MIP">;
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defm : ImageLoadPatterns<int_amdgcn_image_load, "IMAGE_LOAD">;
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defm : ImageLoadPatterns<int_amdgcn_image_load_mip, "IMAGE_LOAD_MIP">;
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defm : ImageStorePatterns<int_amdgcn_image_store, "IMAGE_STORE">;
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defm : ImageStorePatterns<int_amdgcn_image_store_mip, "IMAGE_STORE_MIP">;
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/* SIsample for simple 1D texture lookup */
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def : Pat <
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@ -2420,27 +2450,6 @@ defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16,
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IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16,
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v16i32>;
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/* int_SI_imageload for texture fetches consuming varying address parameters */
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class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
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(name addr_type:$addr, v8i32:$rsrc, imm),
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(opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
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>;
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class ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
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(name addr_type:$addr, v8i32:$rsrc, TEX_ARRAY),
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(opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
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>;
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class ImageLoadMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
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(name addr_type:$addr, v8i32:$rsrc, TEX_MSAA),
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(opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
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>;
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class ImageLoadArrayMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
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(name addr_type:$addr, v8i32:$rsrc, TEX_ARRAY_MSAA),
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(opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
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>;
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/********** ============================================ **********/
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/********** Extraction, Insertion, Building and Casting **********/
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/********** ============================================ **********/
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@ -0,0 +1,111 @@
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;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s
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;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
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;CHECK-LABEL: {{^}}image_load_v4i32:
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;CHECK: image_load v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v[0:3], s[0:7]
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;CHECK: s_waitcnt vmcnt(0)
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define <4 x float> @image_load_v4i32(<8 x i32> inreg %rsrc, <4 x i32> %c) #0 {
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main_body:
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%tex = call <4 x float> @llvm.amdgcn.image.load.v4i32(<4 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
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ret <4 x float> %tex
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}
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;CHECK-LABEL: {{^}}image_load_v2i32:
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;CHECK: image_load v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v[0:1], s[0:7]
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;CHECK: s_waitcnt vmcnt(0)
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define <4 x float> @image_load_v2i32(<8 x i32> inreg %rsrc, <2 x i32> %c) #0 {
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main_body:
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%tex = call <4 x float> @llvm.amdgcn.image.load.v2i32(<2 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
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ret <4 x float> %tex
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}
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;CHECK-LABEL: {{^}}image_load_i32:
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;CHECK: image_load v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v0, s[0:7]
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;CHECK: s_waitcnt vmcnt(0)
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define <4 x float> @image_load_i32(<8 x i32> inreg %rsrc, i32 %c) #0 {
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main_body:
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%tex = call <4 x float> @llvm.amdgcn.image.load.i32(i32 %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
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ret <4 x float> %tex
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}
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;CHECK-LABEL: {{^}}image_load_mip:
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;CHECK: image_load_mip v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v[0:3], s[0:7]
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;CHECK: s_waitcnt vmcnt(0)
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define <4 x float> @image_load_mip(<8 x i32> inreg %rsrc, <4 x i32> %c) #0 {
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main_body:
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%tex = call <4 x float> @llvm.amdgcn.image.load.mip.v4i32(<4 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
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ret <4 x float> %tex
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}
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;CHECK-LABEL: {{^}}image_load_1:
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;CHECK: image_load v0, 1, -1, 0, 0, 0, 0, 0, 0, v[0:3], s[0:7]
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;CHECK: s_waitcnt vmcnt(0)
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define float @image_load_1(<8 x i32> inreg %rsrc, <4 x i32> %c) #0 {
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main_body:
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%tex = call <4 x float> @llvm.amdgcn.image.load.v4i32(<4 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
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%elt = extractelement <4 x float> %tex, i32 0
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; Only first component used, test that dmask etc. is changed accordingly
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ret float %elt
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}
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;CHECK-LABEL: {{^}}image_store_v4i32:
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;CHECK: image_store v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v[4:7], s[0:7]
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define void @image_store_v4i32(<8 x i32> inreg %rsrc, <4 x float> %data, <4 x i32> %coords) #0 {
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main_body:
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call void @llvm.amdgcn.image.store.v4i32(<4 x float> %data, <4 x i32> %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
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ret void
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}
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;CHECK-LABEL: {{^}}image_store_v2i32:
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;CHECK: image_store v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v[4:5], s[0:7]
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define void @image_store_v2i32(<8 x i32> inreg %rsrc, <4 x float> %data, <2 x i32> %coords) #0 {
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main_body:
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call void @llvm.amdgcn.image.store.v2i32(<4 x float> %data, <2 x i32> %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
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ret void
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}
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;CHECK-LABEL: {{^}}image_store_i32:
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;CHECK: image_store v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v4, s[0:7]
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define void @image_store_i32(<8 x i32> inreg %rsrc, <4 x float> %data, i32 %coords) #0 {
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main_body:
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call void @llvm.amdgcn.image.store.i32(<4 x float> %data, i32 %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
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ret void
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}
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;CHECK-LABEL: {{^}}image_store_mip:
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;CHECK: image_store_mip v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v[4:7], s[0:7]
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define void @image_store_mip(<8 x i32> inreg %rsrc, <4 x float> %data, <4 x i32> %coords) #0 {
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main_body:
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call void @llvm.amdgcn.image.store.mip.v4i32(<4 x float> %data, <4 x i32> %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
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ret void
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}
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; Ideally, the register allocator would avoid the wait here
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;
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;CHECK-LABEL: {{^}}image_store_wait:
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;CHECK: image_store v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v4, s[0:7]
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;CHECK: s_waitcnt vmcnt(0) expcnt(0)
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;CHECK: image_load v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v4, s[8:15]
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: image_store v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v4, s[16:23]
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define void @image_store_wait(<8 x i32> inreg, <8 x i32> inreg, <8 x i32> inreg, <4 x float>, i32) #0 {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.i32(<4 x float> %3, i32 %4, <8 x i32> %0, i32 15, i1 0, i1 0, i1 0, i1 0)
|
||||
%data = call <4 x float> @llvm.amdgcn.image.load.i32(i32 %4, <8 x i32> %1, i32 15, i1 0, i1 0, i1 0, i1 0)
|
||||
call void @llvm.amdgcn.image.store.i32(<4 x float> %data, i32 %4, <8 x i32> %2, i32 15, i1 0, i1 0, i1 0, i1 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.amdgcn.image.store.i32(<4 x float>, i32, <8 x i32>, i32, i1, i1, i1, i1) #1
|
||||
declare void @llvm.amdgcn.image.store.v2i32(<4 x float>, <2 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #1
|
||||
declare void @llvm.amdgcn.image.store.v4i32(<4 x float>, <4 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #1
|
||||
declare void @llvm.amdgcn.image.store.mip.v4i32(<4 x float>, <4 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #1
|
||||
|
||||
declare <4 x float> @llvm.amdgcn.image.load.i32(i32, <8 x i32>, i32, i1, i1, i1, i1) #2
|
||||
declare <4 x float> @llvm.amdgcn.image.load.v2i32(<2 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #2
|
||||
declare <4 x float> @llvm.amdgcn.image.load.v4i32(<4 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #2
|
||||
declare <4 x float> @llvm.amdgcn.image.load.mip.v4i32(<4 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #2
|
||||
|
||||
attributes #0 = { "ShaderType"="0" }
|
||||
attributes #1 = { nounwind }
|
||||
attributes #2 = { nounwind readonly }
|
||||
Loading…
Reference in New Issue