forked from OSchip/llvm-project
parent
b076731713
commit
f2bff92411
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@ -892,6 +892,12 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
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return getNode(ISD::SUB, VT, N1, N2.getOperand(0));
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return getNode(ISD::SUB, VT, N1, N2.getOperand(0));
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if (N1.getOpcode() == ISD::FNEG) // ((-A)+B) -> B-A
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if (N1.getOpcode() == ISD::FNEG) // ((-A)+B) -> B-A
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return getNode(ISD::SUB, VT, N2, N1.getOperand(0));
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return getNode(ISD::SUB, VT, N2, N1.getOperand(0));
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if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
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cast<ConstantSDNode>(N1.getOperand(0))->getValue() == 0)
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return getNode(ISD::SUB, VT, N2, N1.getOperand(1)); // (0-A)+B -> B-A
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if (N2.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N2.getOperand(0)) &&
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cast<ConstantSDNode>(N2.getOperand(0))->getValue() == 0)
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return getNode(ISD::SUB, VT, N1, N2.getOperand(1)); // A+(0-B) -> A-B
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break;
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break;
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case ISD::SUB:
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case ISD::SUB:
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if (N1.getOpcode() == ISD::ADD) {
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if (N1.getOpcode() == ISD::ADD) {
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