forked from OSchip/llvm-project
ScheduleDAGInstrs: Ignore dependencies of constant physregs
There is no need to track dependencies for constant physregs, as they don't change their value no matter in what order you read/write to them. Differential Revision: https://reviews.llvm.org/D26221 llvm-svn: 286526
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@ -323,6 +323,9 @@ void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
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MachineInstr *MI = SU->getInstr();
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MachineInstr *MI = SU->getInstr();
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MachineOperand &MO = MI->getOperand(OperIdx);
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MachineOperand &MO = MI->getOperand(OperIdx);
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unsigned Reg = MO.getReg();
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unsigned Reg = MO.getReg();
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// We do not need to track any dependencies for constant registers.
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if (MRI.isConstantPhysReg(Reg))
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return;
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// Optionally add output and anti dependencies. For anti
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// Optionally add output and anti dependencies. For anti
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// dependencies we use a latency of 0 because for a multi-issue
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// dependencies we use a latency of 0 because for a multi-issue
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@ -8,8 +8,8 @@ define i64 @csed-impdef-killflag(i64 %a) {
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; CHECK-DAG: orr [[REG1:w[0-9]+]], wzr, #0x1
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; CHECK-DAG: orr [[REG1:w[0-9]+]], wzr, #0x1
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; CHECK-DAG: orr [[REG2:x[0-9]+]], xzr, #0x2
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; CHECK-DAG: orr [[REG2:x[0-9]+]], xzr, #0x2
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; CHECK-DAG: orr [[REG3:x[0-9]+]], xzr, #0x3
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; CHECK-DAG: orr [[REG3:x[0-9]+]], xzr, #0x3
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; CHECK: cmp x0, #0
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; CHECK-DAG: cmp x0, #0
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; CHECK-DAG: csel w[[SELECT_WREG_1:[0-9]+]], wzr, [[REG1]], ne
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; CHECK: csel w[[SELECT_WREG_1:[0-9]+]], wzr, [[REG1]], ne
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; CHECK-DAG: csel [[SELECT_XREG_2:x[0-9]+]], [[REG2]], [[REG3]], ne
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; CHECK-DAG: csel [[SELECT_XREG_2:x[0-9]+]], [[REG2]], [[REG3]], ne
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; CHECK: ubfx [[SELECT_XREG_1:x[0-9]+]], x[[SELECT_WREG_1]], #0, #32
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; CHECK: ubfx [[SELECT_XREG_1:x[0-9]+]], x[[SELECT_WREG_1]], #0, #32
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; CHECK-NEXT: add x0, [[SELECT_XREG_2]], [[SELECT_XREG_1]]
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; CHECK-NEXT: add x0, [[SELECT_XREG_2]], [[SELECT_XREG_1]]
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@ -0,0 +1,29 @@
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# RUN: llc -o /dev/null %s -mtriple=aarch64-- -run-pass=machine-scheduler -enable-misched -debug-only=misched 2>&1 | FileCheck %s
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# REQUIRES: asserts
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--- |
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define void @func() { ret void }
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...
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---
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# Check that the instructions are not dependent on each other, even though
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# they all read/write to the zero register.
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# CHECK-LABEL: MI Scheduling
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# CHECK: SU(0): %WZR<def,dead> = SUBSWri %W1, 0, 0, %NZCV<imp-def,dead>
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# CHECK: # succs left : 0
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# CHECK-NOT: Successors:
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# CHECK: SU(1): %W2<def> = COPY %WZR
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# CHECK: # succs left : 0
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# CHECK-NOT: Successors:
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# CHECK: SU(2): %WZR<def,dead> = SUBSWri %W3, 0, 0, %NZCV<imp-def,dead>
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# CHECK: # succs left : 0
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# CHECK-NOT: Successors:
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# CHECK: SU(3): %W4<def> = COPY %WZR
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# CHECK: # succs left : 0
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# CHECK-NOT: Successors:
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name: func
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body: |
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bb.0:
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dead %wzr = SUBSWri %w1, 0, 0, implicit-def dead %nzcv
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%w2 = COPY %wzr
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dead %wzr = SUBSWri %w3, 0, 0, implicit-def dead %nzcv
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%w4 = COPY %wzr
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...
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@ -7,7 +7,7 @@
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define i32 @test01() nounwind {
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define i32 @test01() nounwind {
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; CHECK: ldrb {{.*}}
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; CHECK: ldrb {{.*}}
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; CHECK-NEXT: ldrb {{.*}}
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; CHECK-NEXT: ldrb {{.*}}
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; CHECK-NEXT: sub {{.*}}
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; CHECK: sub {{.*}}
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; CHECK-NEXT: cmn {{.*}}
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; CHECK-NEXT: cmn {{.*}}
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entry:
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entry:
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%0 = load i8, i8* @a, align 1
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%0 = load i8, i8* @a, align 1
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