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[X86] Improve use of SHLD/SHRD 

Summary:
This extends the variety of pattern that can generate a SHLD instead of using two shifts.

This fixes a regression that would be introduced by D57367 or D33587

Reviewers: RKSimon, craig.topper

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D57389

llvm-svn: 355260
This commit is contained in:
Amaury Sechet 2019-03-02 02:44:16 +00:00
parent 98f11a7d75
commit f24abf6511
3 changed files with 15 additions and 25 deletions
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6
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -37425,6 +37425,12 @@ static SDValue combineOr(SDNode *N, SelectionDAG &DAG,
SDValue Sum = ShAmt1.getOperand(0);
if (auto *SumC = dyn_cast<ConstantSDNode>(Sum)) {
SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
if (ShAmt1Op1.getOpcode() == ISD::AND &&
isa<ConstantSDNode>(ShAmt1Op1.getOperand(1)) &&
ShAmt1Op1.getConstantOperandVal(1) == (Bits - 1)) {
ShMsk1 = ShAmt1Op1;
ShAmt1Op1 = ShAmt1Op1.getOperand(0);
}
if (ShAmt1Op1.getOpcode() == ISD::TRUNCATE)
ShAmt1Op1 = ShAmt1Op1.getOperand(0);
if ((SumC->getAPIntValue() == Bits ||

10
llvm/test/CodeGen/X86/shift-double-x86_64.ll
View File

@ -118,14 +118,10 @@ define i64 @test7(i64 %hi, i64 %lo, i64 %bits) nounwind {
define i64 @test8(i64 %hi, i64 %lo, i64 %bits) nounwind {
; CHECK-LABEL: test8:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdx, %rcx
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: movl %edx, %ecx
; CHECK-NEXT: andb $63, %cl
; CHECK-NEXT: negb %cl
; CHECK-NEXT: shrq %cl, %rsi
; CHECK-NEXT: movl %edx, %ecx
; CHECK-NEXT: shlq %cl, %rax
; CHECK-NEXT: orq %rsi, %rax
; CHECK-NEXT: # kill: def $cl killed $cl killed $rcx
; CHECK-NEXT: shldq %cl, %rsi, %rax
; CHECK-NEXT: retq
%tbits = trunc i64 %bits to i8
%tand = and i8 %tbits, 63

24
llvm/test/CodeGen/X86/shift-double.ll
View File

@ -462,30 +462,18 @@ define i32 @test17(i32 %hi, i32 %lo, i32 %bits) nounwind {
define i32 @test18(i32 %hi, i32 %lo, i32 %bits) nounwind {
; X86-LABEL: test18:
; X86: # %bb.0:
; X86-NEXT: pushl %esi
; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-NEXT: movl %edx, %ecx
; X86-NEXT: andb $31, %cl
; X86-NEXT: negb %cl
; X86-NEXT: shrl %cl, %esi
; X86-NEXT: movl %edx, %ecx
; X86-NEXT: shll %cl, %eax
; X86-NEXT: orl %esi, %eax
; X86-NEXT: popl %esi
; X86-NEXT: shldl %cl, %edx, %eax
; X86-NEXT: retl
;
; X64-LABEL: test18:
; X64: # %bb.0:
; X64-NEXT: movl %edx, %ecx
; X64-NEXT: movl %edi, %eax
; X64-NEXT: movl %edx, %ecx
; X64-NEXT: andb $31, %cl
; X64-NEXT: negb %cl
; X64-NEXT: shrl %cl, %esi
; X64-NEXT: movl %edx, %ecx
; X64-NEXT: shll %cl, %eax
; X64-NEXT: orl %esi, %eax
; X64-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NEXT: shldl %cl, %esi, %eax
; X64-NEXT: retq
%tbits = trunc i32 %bits to i8
%tand = and i8 %tbits, 31