forked from OSchip/llvm-project
parent
1ab7eac84b
commit
f228c95f87
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@ -1715,6 +1715,9 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
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setMinFunctionAlignment(2);
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setStackPointerRegisterToSaveRestore(HRI.getStackRegister());
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setMaxAtomicSizeInBitsSupported(64);
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setMinCmpXchgSizeInBits(32);
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if (EnableHexSDNodeSched)
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setSchedulingPreference(Sched::VLIW);
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else
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@ -3121,3 +3124,10 @@ bool HexagonTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
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// Do not expand loads and stores that don't exceed 64 bits.
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return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() > 64;
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}
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bool HexagonTargetLowering::shouldExpandAtomicCmpXchgInIR(
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AtomicCmpXchgInst *AI) const {
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const DataLayout &DL = AI->getModule()->getDataLayout();
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unsigned Size = DL.getTypeStoreSize(AI->getCompareOperand()->getType());
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return Size >= 4 && Size <= 8;
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}
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@ -256,6 +256,8 @@ bool isPositiveHalfWord(SDNode *N);
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Value *Addr, AtomicOrdering Ord) const override;
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AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
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bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
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bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
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AtomicExpansionKind
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shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override {
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return AtomicExpansionKind::LLSC;
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@ -69,3 +69,16 @@ entry:
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return: ; preds = %entry
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ret void
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}
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define i64 @fred() nounwind {
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entry:
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%s0 = cmpxchg i32* undef, i32 undef, i32 undef seq_cst seq_cst
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%s1 = extractvalue { i32, i1 } %s0, 0
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%t0 = cmpxchg i64* undef, i64 undef, i64 undef seq_cst seq_cst
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%t1 = extractvalue { i64, i1 } %t0, 0
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%u0 = zext i32 %s1 to i64
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%u1 = add i64 %u0, %t1
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ret i64 %u1
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}
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