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Eliminate the distinction between "real" and "unreal" instructions 

llvm-svn: 11986
This commit is contained in:
Chris Lattner 2004-02-29 06:31:16 +00:00
parent e65125dcdf
commit f20abac9bc
3 changed files with 7 additions and 9 deletions
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10
llvm/include/llvm/Target/TargetInstrInfo.h
View File

@ -83,27 +83,25 @@ struct TargetInstrDescriptor {
/// ///
class TargetInstrInfo { class TargetInstrInfo {
const TargetInstrDescriptor* desc; // raw array to allow static init'n const TargetInstrDescriptor* desc; // raw array to allow static init'n
unsigned descSize; // number of entries in the desc array unsigned NumOpcodes; // number of entries in the desc array
unsigned numRealOpCodes; // number of non-dummy op codes unsigned numRealOpCodes; // number of non-dummy op codes
TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
public: public:
TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned descSize, TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
unsigned numRealOpCodes);
virtual ~TargetInstrInfo(); virtual ~TargetInstrInfo();
// Invariant: All instruction sets use opcode #0 as the PHI instruction // Invariant: All instruction sets use opcode #0 as the PHI instruction
enum { PHI = 0 }; enum { PHI = 0 };
unsigned getNumRealOpCodes() const { return numRealOpCodes; } unsigned getNumOpcodes() const { return NumOpcodes; }
unsigned getNumTotalOpCodes() const { return descSize; }
/// get - Return the machine instruction descriptor that corresponds to the /// get - Return the machine instruction descriptor that corresponds to the
/// specified instruction opcode. /// specified instruction opcode.
/// ///
const TargetInstrDescriptor& get(MachineOpCode opCode) const { const TargetInstrDescriptor& get(MachineOpCode opCode) const {
assert(opCode >= 0 && opCode < (int)descSize); assert((unsigned)opCode < NumOpcodes);
return desc[opCode]; return desc[opCode];
} }

2
llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp
View File

@ -520,7 +520,7 @@ SchedulingManager::SchedulingManager(const TargetMachine& target,
nextEarliestIssueTime(0), nextEarliestIssueTime(0),
choicesForSlot(nslots), choicesForSlot(nslots),
numInClass(target.getSchedInfo().getNumSchedClasses(), 0), // set all to 0 numInClass(target.getSchedInfo().getNumSchedClasses(), 0), // set all to 0
nextEarliestStartTime(target.getInstrInfo().getNumRealOpCodes(), nextEarliestStartTime(target.getInstrInfo().getNumOpcodes(),
(cycles_t) 0) // set all to 0 (cycles_t) 0) // set all to 0
{ {
updateTime(0); updateTime(0);

4
llvm/lib/Target/TargetSchedInfo.cpp
View File

@ -119,7 +119,7 @@ void
TargetSchedInfo::computeInstrResources(const std::vector<InstrRUsage>& TargetSchedInfo::computeInstrResources(const std::vector<InstrRUsage>&
instrRUForClasses) instrRUForClasses)
{ {
int numOpCodes = mii->getNumRealOpCodes(); int numOpCodes = mii->getNumOpcodes();
instrRUsages.resize(numOpCodes); instrRUsages.resize(numOpCodes);
// First get the resource usage information from the class resource usages. // First get the resource usage information from the class resource usages.
@ -149,7 +149,7 @@ void
TargetSchedInfo::computeIssueGaps(const std::vector<InstrRUsage>& TargetSchedInfo::computeIssueGaps(const std::vector<InstrRUsage>&
instrRUForClasses) instrRUForClasses)
{ {
int numOpCodes = mii->getNumRealOpCodes(); int numOpCodes = mii->getNumOpcodes();
issueGaps.resize(numOpCodes); issueGaps.resize(numOpCodes);
conflictLists.resize(numOpCodes); conflictLists.resize(numOpCodes);